Hi Dirk,
On Tue, Jun 17, 2014 at 9:18 AM, Dirk Eibach <dirk.eib...@gdsys.cc> wrote:
> Heh. Good catch. thanks!
> But now I'm curious: how did you find this?
>
> Acked-by: dirk.eib...@gdsys.cc
>
> Cheers
> Dirk
I had the following compiler warning (and I actually don't understand
why it was generated here):
In file included from /home/lab/dev/uboot/board/gdsys/405ex/io64.c:25:0:
/home/lab/dev/uboot/board/gdsys/405ex/io64.c: In function 'last_stage_init':
/home/lab/dev/uboot/include/gdsys_fpga.h:35:17: warning: iteration 2u
invokes undefined behavior [-Waggressive-loop-optimizations]
&fpga_ptr[ix]->fld, \
^
/home/lab/dev/uboot/board/gdsys/405ex/io64.c:307:4: note: in expansion
of macro 'FPGA_GET_REG'
FPGA_GET_REG(k, hicb_ch[k].status_int, &status);
^
/home/lab/dev/uboot/board/gdsys/405ex/io64.c:305:3: note: containing loop
for (k = 0; k < 32; ++k) {
^
So I had to look on the code...
Best,
Vasili
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