On 05/15/2014 07:52 PM, shh....@gmail.com wrote: > From: Shaohui Xie <shaohui....@freescale.com> > > A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to > increase and cause the PLL to unlock when the temperature delta from the > time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V > (or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC > VCO. Only the protocols using Ring VCOs are impacted. > > Workaround: > For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need > to use alternate serdes protocols. The alternate option has the same > functionality as the original option; the only difference being LC VCO > rather than Ring VCO. > > Signed-off-by: Shaohui Xie <shaohui....@freescale.com> > --- > changes for V3: > update t4_rcw.cfg. > > changes for V2: > refined commit message. >
Applied to u-boot-mpc85xx. Sorry for the late notice. York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
