The CPCI750 can be built as CPCI host or adapter/target board. This patch
adds support for runtime detection of those variants.
Signed-off-by: Stefan Roese <s...@denx.de>
Cc: Reinhard Arlt <reinhard.a...@esd-electronics.com>
---
board/esd/cpci750/cpci750.c | 108 +++++++++++++++++++++++++++++++++++++++----
board/esd/cpci750/ide.c | 4 +-
board/esd/cpci750/pci.c | 57 ++++++++++++++++------
include/configs/CPCI750.h | 5 ++-
4 files changed, 147 insertions(+), 27 deletions(-)
diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
index 4826633..6641304 100644
--- a/board/esd/cpci750/cpci750.c
+++ b/board/esd/cpci750/cpci750.c
@@ -122,6 +122,9 @@ static char show_config_tab[][15] = {{"PCI0DLL_2 "},
/* 31 */
extern flash_info_t flash_info[];
+extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
+extern int do_bootvx (cmd_tbl_t *, int, int, char *[]);
+
/* ------------------------------------------------------------------------- */
/* this is the current GT register space location */
@@ -137,6 +140,15 @@ void board_prebootm_init (void);
unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
int display_mem_map (void);
+/*
+ * Skip video initialization on slave variant.
+ * This function will overwrite the weak default in ct6900.c
+ */
+int board_video_skip(void)
+{
+ return CPCI750_SLAVE_TEST;
+}
+
/* ------------------------------------------------------------------------- */
/*
@@ -184,6 +196,7 @@ original ppcboot 1.1.6 source end */
static void gt_pci_config (void)
{
unsigned int stat;
+ unsigned int data;
unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11,
FuncNum 10:8, RegNum 7:2 */
/* In PCIX mode devices provide their own bus and device numbers. We
query the Discovery II's
@@ -251,10 +264,11 @@ static void gt_pci_config (void)
/*ronen update the pci internal registers base address.*/
#ifdef MAP_PCI
- for (stat = 0; stat <= PCI_HOST1; stat++)
- pciWriteConfigReg (stat,
-
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
- SELF, CONFIG_SYS_GT_REGS);
+ for (stat = 0; stat <= PCI_HOST1; stat++) {
+ data = pciReadConfigReg(stat,
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, SELF);
+ data = (data & 0x0f) | CONFIG_SYS_GT_REGS;
+ pciWriteConfigReg (stat,
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, SELF, data);
+ }
#endif
}
@@ -448,13 +462,16 @@ int misc_init_r ()
void after_reloc (ulong dest_addr, gd_t * gd)
{
+ memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE,
+ CONFIG_SYS_BOOT_SIZE);
- memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE,
CONFIG_SYS_BOOT_SIZE);
+ display_mem_map ();
+ GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
+ GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
- display_mem_map ();
- /* now, jump to the main ppcboot board init code */
- board_init_r (gd, dest_addr);
- /* NOTREACHED */
+ /* now, jump to the main ppcboot board init code */
+ board_init_r (gd, dest_addr);
+ /* NOTREACHED */
}
/* ------------------------------------------------------------------------- */
@@ -538,6 +555,79 @@ int display_mem_map (void)
return (0);
}
+/*
+ * Command loadpci: wait for signal from host and boot image.
+ */
+int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ volatile unsigned int *ptr;
+ int count = 0;
+ int count2 = 0;
+ int status;
+ char addr[16];
+ char str[] = "\\|/-";
+ char *local_args[2];
+
+ /*
+ * Mark sync address
+ */
+ ptr = 0;
+ ptr[0] = 0xffffffff;
+ ptr[1] = 0xffffffff;
+ puts("\nWaiting for image from pci host -");
+
+ /*
+ * Wait for host to write the start address
+ */
+ while (*ptr == 0xffffffff) {
+ count++;
+ if (!(count % 100)) {
+ count2++;
+ putc(0x08); /* backspace */
+ putc(str[count2 % 4]);
+ }
+
+ /* Abort if ctrl-c was pressed */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ return 0;
+ }
+
+ udelay(1000);
+ }
+
+ sprintf(addr, "%08x", *ptr);
+ printf("\nBooting Image at addr 0x%s ...\n", addr);
+ setenv("loadaddr", addr);
+
+ switch (ptr[1] == 0) {
+ case 0:
+ /*
+ * Boot image via bootm
+ */
+ local_args[0] = argv[0];
+ local_args[1] = NULL;
+ status = do_bootm (cmdtp, 0, 1, local_args);
+ break;
+ case 1:
+ /*
+ * Boot image via bootvx
+ */
+ local_args[0] = argv[0];
+ local_args[1] = NULL;
+ status = do_bootvx (cmdtp, 0, 1, local_args);
+ break;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ loadpci, 1, 1, do_loadpci,
+ "loadpci - Wait for pci-image and boot it\n",
+ NULL
+ );
+
/* DRAM check routines copied from gw8260 */
#if defined (CONFIG_SYS_DRAM_TEST)
diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c
index 9bdc523..8ec2346 100644
--- a/board/esd/cpci750/ide.c
+++ b/board/esd/cpci750/ide.c
@@ -39,6 +39,8 @@ int ide_preinit (void)
int l;
status = 1;
+ if (CPCI750_SLAVE_TEST != 0)
+ return status;
for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
ide_bus_offset[l] = -ATA_STATUS;
}
@@ -57,7 +59,7 @@ int ide_preinit (void)
ide_bus_offset[1] &= 0xfffffffe;
ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE;
}
- return (status);
+ return status;
}
void ide_set_reset (int flag) {
diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c
index bfc7e55..552ad92 100644
--- a/board/esd/cpci750/pci.c
+++ b/board/esd/cpci750/pci.c
@@ -768,7 +768,8 @@ static int gt_read_config_dword (struct pci_controller
*hose,
int bus = PCI_BUS (dev);
if ((bus == local_buses[0]) || (bus == local_buses[1])) {
- *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+ *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr,
+ offset | (PCI_FUNC(dev) << 8),
PCI_DEV (dev));
} else {
*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
@@ -785,11 +786,13 @@ static int gt_write_config_dword (struct pci_controller
*hose,
int bus = PCI_BUS (dev);
if ((bus == local_buses[0]) || (bus == local_buses[1])) {
- pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+ pciWriteConfigReg ((PCI_HOST) hose->cfg_addr,
+ offset | (PCI_FUNC(dev) << 8),
PCI_DEV (dev), value);
} else {
pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
- offset, PCI_DEV (dev), bus,
+ offset | (PCI_FUNC(dev) << 8),
+ PCI_DEV (dev), bus,
value);
}
return 0;
@@ -803,6 +806,9 @@ static void gt_setup_ide (struct pci_controller *hose,
u32 bar_response, bar_value;
int bar;
+ if (CPCI750_SLAVE_TEST != 0)
+ return;
+
for (bar = 0; bar < 6; bar++) {
/*ronen different function for 3rd bank. */
unsigned int offset =
@@ -829,6 +835,9 @@ static void gt_setup_cpcidvi (struct pci_controller *hose,
{
u32 bar_value, pci_response;
+ if (CPCI750_SLAVE_TEST != 0)
+ return;
+
pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0,
&pci_response);
@@ -907,6 +916,7 @@ struct pci_controller pci1_hose = {
void pci_init_board (void)
{
unsigned int command;
+ unsigned int slave;
#ifdef CONFIG_PCI_PNP
unsigned int bar;
#endif
@@ -918,6 +928,8 @@ void pci_init_board (void)
gt_cpcidvi_rom.base = 0;
#endif
+ slave = CPCI750_SLAVE_TEST;
+
pci0_hose.config_table = gt_config_table;
pci1_hose.config_table = gt_config_table;
@@ -953,27 +965,40 @@ void pci_init_board (void)
pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
pci_register_hose (&pci0_hose);
- pciArbiterEnable (PCI_HOST0);
- pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
- command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MASTER;
- pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
- command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MEMORY;
- pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+ if (slave == 0) {
+ pciArbiterEnable (PCI_HOST0);
+ pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+ command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+ command |= PCI_COMMAND_MASTER;
+ pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+ command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+ command |= PCI_COMMAND_MEMORY;
+ pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
#ifdef CONFIG_PCI_PNP
- pciauto_config_init(&pci0_hose);
- pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
+ pciauto_config_init(&pci0_hose);
+ pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
#endif
#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
+ printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
- pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose,
pci0_hose.first_busno);
+ pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose,
+
pci0_hose.first_busno);
#ifdef DEBUG
- gt_pci_bus_mode_display (PCI_HOST1);
+ gt_pci_bus_mode_display (PCI_HOST1);
#endif
+ } else {
+ pciArbiterDisable (PCI_HOST0);
+ pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+ command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+ command |= PCI_COMMAND_MASTER;
+ pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+ command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+ command |= PCI_COMMAND_MEMORY;
+ pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+ pci0_hose.last_busno = pci0_hose.first_busno;
+ }
pci1_hose.first_busno = pci0_hose.last_busno + 1;
pci1_hose.last_busno = 0xff;
pci1_hose.current_busno = pci1_hose.first_busno;
diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h
index 8494faa..d516c3c 100644
--- a/include/configs/CPCI750.h
+++ b/include/configs/CPCI750.h
@@ -76,7 +76,8 @@
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_AUTO_COMPLETE 1
+#define CONFIG_CMDLINE_EDITING /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Define which ETH port will be used for connecting the network */
#define CONFIG_SYS_ETH_PORT ETH_0
@@ -626,4 +627,6 @@
#define CONFIG_SYS_BOARD_ASM_INIT 1
+#define CPCI750_SLAVE_TEST (((in8(0xf0300000) & 0x80) == 0) ? 0 : 1)
+
#endif /* __CONFIG_H */
--
1.6.2.5
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