On Mon, May 5, 2014 at 3:34 AM, Stefano Babic <sba...@denx.de> wrote:
> Hi Tim,
>
> On 28/04/2014 22:17, Tim Harvey wrote:
>> Add memory-mapped structures for MMDC iomux and configuration. Note that
>> while
>> the MMDC configuration registers are common between the IMX6DQ
>> (IMX6DUAL/IMX6QUAD) and IMX6SDL (IMX6SOLO/IMX6DUALLITE) types the iomux
>> registers differ. This requires two sets of structures.
>>
>> Add structures to describe DDR3 device information, system information
>> (memory layout, etc), and MMDC calibration regitsers that can be used to
>> configure the MMDC dynamically.
>>
>> We define these structures for SPL builds instead of including mx6q-ddr.h and
>> mx6dl-ddr.h which use the same namespace and are only useful for imximage cfg
>> files.
>>
>> Signed-off-by: Tim Harvey <thar...@gateworks.com>
>> ---
>> v2:
>> - split out from original mmdc configuration patch
>> - only define for SPL build
>> - do not include mx6q-ddr.h and mx6dl-ddr.h for SPL build - these use the
>> same namespace and are only useful for imximage cfg files
>> ---
>> arch/arm/include/asm/arch-mx6/mx6-ddr.h | 231
>> ++++++++++++++++++++++++++++++++
>> 1 file changed, 231 insertions(+)
>>
>> diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
>> b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
>> index 43d377a..d544d2e 100644
>> --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
>> +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
>> @@ -6,6 +6,7 @@
>> #ifndef __ASM_ARCH_MX6_DDR_H__
>> #define __ASM_ARCH_MX6_DDR_H__
>>
>> +#ifndef CONFIG_SPL_BUILD
>> #ifdef CONFIG_MX6Q
>> #include "mx6q-ddr.h"
>> #else
>> @@ -15,6 +16,236 @@
>> #error "Please select cpu"
>> #endif /* CONFIG_MX6DL or CONFIG_MX6S */
>> #endif /* CONFIG_MX6Q */
>> +#else
>> +
>> +/* MMDC P0/P1 Registers */
>> +struct mmdc_p_regs {
>> + u32 mdctl;
>> + u32 mdpdc;
>> + u32 mdotc;
>> + u32 mdcfg0;
>> + u32 mdcfg1;
>> + u32 mdcfg2;
>> + u32 mdmisc;
>> + u32 mdscr;
>> + u32 mdref;
>> + u32 res1[2];
>> + u32 mdrwd;
>> + u32 mdor;
>> + u32 res2[3];
>> + u32 mdasp;
>> + u32 res3[240];
>> + u32 mapsr;
>> + u32 res4[254];
>> + u32 mpzqhwctrl;
>> + u32 res5[2];
>> + u32 mpwldectrl0;
>> + u32 mpwldectrl1;
>> + u32 res6;
>> + u32 mpodtctrl;
>> + u32 mprddqby0dl;
>> + u32 mprddqby1dl;
>> + u32 mprddqby2dl;
>> + u32 mprddqby3dl;
>> + u32 res7[4];
>> + u32 mpdgctrl0;
>> + u32 mpdgctrl1;
>> + u32 res8;
>> + u32 mprddlctl;
>> + u32 res9;
>> + u32 mpwrdlctl;
>> + u32 res10[25];
>> + u32 mpmur0;
>> +};
>> +
>> +/*
>> + * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
>> + */
>> +#define MX6DQ_IOM_DDR_BASE 0x020e0500
>
> It is only a question - having the value here let us know where the
> registers are located. Anyway, registers' offsets are stored in the
> imx-regs.h file of the SOC. Which is the reason to set them here ?
I felt they belonged with the ddr structures themselves. I can move
them but then will someone claim that the ddr structures should also
be moved?
Tim
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