Hello Dongsheng, We do have requirement to support this that's why code development was done. Also , what is the dependency of deep-sleep on this. Please elaborate And if something is broken, we should fix it. Instead of removing the feature.
Regards Priyanka > -----Original Message----- > From: Dongsheng Wang [mailto:dongsheng.w...@freescale.com] > Sent: Friday, April 18, 2014 1:09 PM > To: Sun York-R58495 > Cc: Jain Priyanka-B32167; Wood Scott-B07421; u-boot@lists.denx.de; Wang > Dongsheng-B40534 > Subject: [PATCH] powerpc/t1040qds: Remove Video - HDMI support > > From: Wang Dongsheng <dongsheng.w...@freescale.com> > > We should remove this support. > First, there is not any documents to say we need to support this feature, > and kernel also not support this feature. > Second, Kerneal not support this on T1040QDS, so if we open it in u-boot, > FPGA will be changed and that will affect deep sleep feature. > > Signed-off-by: Wang Dongsheng <dongsheng.w...@freescale.com> > > diff --git a/board/freescale/t1040qds/Makefile > b/board/freescale/t1040qds/Makefile > index 19ed21b..c7470d7 100644 > --- a/board/freescale/t1040qds/Makefile > +++ b/board/freescale/t1040qds/Makefile > @@ -10,4 +10,3 @@ obj-$(CONFIG_PCI) += pci.o > obj-y += law.o > obj-y += tlb.o > obj-y += eth.o > -obj-y += diu.o > diff --git a/board/freescale/t1040qds/diu.c > b/board/freescale/t1040qds/diu.c deleted file mode 100644 index > 0214224..0000000 > --- a/board/freescale/t1040qds/diu.c > +++ /dev/null > @@ -1,97 +0,0 @@ > -/* > - * Copyright 2014 Freescale Semiconductor, Inc. > - * Author: Priyanka Jain <priyanka.j...@freescale.com> > - * > - * SPDX-License-Identifier: GPL-2.0+ > - */ > - > -#include <common.h> > -#include <command.h> > -#include <linux/ctype.h> > -#include <asm/io.h> > -#include <stdio_dev.h> > -#include <video_fb.h> > -#include <fsl_diu_fb.h> > -#include "../common/qixis.h" > -#include "../common/diu_ch7301.h" > -#include "t1040qds.h" > -#include "t1040qds_qixis.h" > - > -/* > - * DIU Area Descriptor > - * > - * Note that we need to byte-swap the value before it's written to the > AD > - * register. So even though the registers don't look like they're in > the same > - * bit positions as they are on the MPC8610, the same value is written > to the > - * AD register on the MPC8610 and on the P1022. > - */ > -#define AD_BYTE_F 0x10000000 > -#define AD_ALPHA_C_SHIFT 25 > -#define AD_BLUE_C_SHIFT 23 > -#define AD_GREEN_C_SHIFT 21 > -#define AD_RED_C_SHIFT 19 > -#define AD_PIXEL_S_SHIFT 16 > -#define AD_COMP_3_SHIFT 12 > -#define AD_COMP_2_SHIFT 8 > -#define AD_COMP_1_SHIFT 4 > -#define AD_COMP_0_SHIFT 0 > - > -void diu_set_pixel_clock(unsigned int pixclock) -{ > - unsigned long speed_ccb, temp; > - u32 pixval; > - int ret = 0; > - speed_ccb = get_bus_freq(0); > - temp = 1000000000 / pixclock; > - temp *= 1000; > - pixval = speed_ccb / temp; > - > - /* Program HDMI encoder */ > - /* Switch channel to DIU */ > - select_i2c_ch_pca9547(I2C_MUX_CH_DIU); > - > - /* Set dispaly encoder */ > - ret = diu_set_dvi_encoder(temp); > - if (ret) { > - puts("Failed to set DVI encoder\n"); > - return; > - } > - > - /* Switch channel to default */ > - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); > - > - /* Program pixel clock */ > - out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, > - ((pixval << PXCK_BITS_START) & PXCK_MASK)); > - /* enable clock*/ > - out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK | > - ((pixval << PXCK_BITS_START) & PXCK_MASK)); > -} > - > -int platform_diu_init(unsigned int xres, unsigned int yres, const char > *port) -{ > - u32 pixel_format; > - u8 sw; > - > - /*Route I2C4 to DIU system as HSYNC/VSYNC*/ > - sw = QIXIS_READ(brdcfg[5]); > - QIXIS_WRITE(brdcfg[5], > - ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU))); > - > - /*Configure Display ouput port as HDMI*/ > - sw = QIXIS_READ(brdcfg[15]); > - QIXIS_WRITE(brdcfg[15], > - ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK)) > - | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI))); > - > - pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | > - (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | > - (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | > - (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | > - (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); > - > - printf("DIU: Switching to monitor @ %ux%u\n", xres, yres); > - > - > - return fsl_diu_init(xres, yres, pixel_format, 0); > -} > diff --git a/board/freescale/t1040qds/t1040qds.h > b/board/freescale/t1040qds/t1040qds.h > index 5041f37..79bdeda 100644 > --- a/board/freescale/t1040qds/t1040qds.h > +++ b/board/freescale/t1040qds/t1040qds.h > @@ -9,6 +9,5 @@ > > void fdt_fixup_board_enet(void *blob); > void pci_of_setup(void *blob, bd_t *bd); -int select_i2c_ch_pca9547(u8 > ch); > > #endif > diff --git a/board/freescale/t1040qds/t1040qds_qixis.h > b/board/freescale/t1040qds/t1040qds_qixis.h > index 98d2d39..2ce8795 100644 > --- a/board/freescale/t1040qds/t1040qds_qixis.h > +++ b/board/freescale/t1040qds/t1040qds_qixis.h > @@ -13,18 +13,6 @@ > #define BRDCFG4_EMISEL_MASK 0xE0 > #define BRDCFG4_EMISEL_SHIFT 5 > > -/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/ > -#define BRDCFG5_IMX_MASK 0xC0 > -#define BRDCFG5_IMX_DIU 0x80 > - > -/* BRDCFG15[3] controls LCD Panel Powerdown*/ > -#define BRDCFG15_LCDPD_MASK 0x10 > -#define BRDCFG15_LCDPD_ENABLED 0x00 > - > -/* BRDCFG15[6:7] controls DIU MUX selction*/ > -#define BRDCFG15_DIUSEL_MASK 0x03 > -#define BRDCFG15_DIUSEL_HDMI 0x00 > - > /* SYSCLK */ > #define QIXIS_SYSCLK_66 0x0 > #define QIXIS_SYSCLK_83 0x1 > diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h > index f4c8547..61bffce 100644 > --- a/include/configs/T1040QDS.h > +++ b/include/configs/T1040QDS.h > @@ -375,7 +375,7 @@ unsigned long get_board_ddr_clk(void); > #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET > > #define CONFIG_SYS_MONITOR_LEN (512 * 1024) > -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) > +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) > > /* Serial Port - controlled on board with jumper J8 > * open - index 2 > @@ -401,26 +401,6 @@ unsigned long get_board_ddr_clk(void); #define > CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " > > -/* Video */ > -#define CONFIG_FSL_DIU_FB > -#ifdef CONFIG_FSL_DIU_FB > -#define CONFIG_FSL_DIU_CH7301 > -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) > -#define CONFIG_VIDEO > -#define CONFIG_CMD_BMP > -#define CONFIG_CFB_CONSOLE > -#define CONFIG_VIDEO_SW_CURSOR > -#define CONFIG_VGA_AS_SINGLE_DEVICE > -#define CONFIG_VIDEO_LOGO > -#define CONFIG_VIDEO_BMP_LOGO > -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS > -/* > - * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, > so > - * disable empty flash sector detection, which is I/O-intensive. > - */ > -#undef CONFIG_SYS_FLASH_EMPTY_INFO > -#endif > - > /* pass open firmware flat tree */ > #define CONFIG_OF_LIBFDT > #define CONFIG_OF_BOARD_SETUP > @@ -446,11 +426,6 @@ unsigned long get_board_ddr_clk(void); > > /* I2C bus multiplexer */ > #define I2C_MUX_CH_DEFAULT 0x8 > -#define I2C_MUX_CH_DIU 0xC > - > -/* LDI/DVI Encoder for display */ > -#define CONFIG_SYS_I2C_LDI_ADDR 0x38 > -#define CONFIG_SYS_I2C_DVI_ADDR 0x75 > > /* > * RTC configuration > @@ -728,7 +703,6 @@ unsigned long get_board_ddr_clk(void); > "bank_intlv=cs0_cs1;" \ > "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ > "netdev=eth0\0" \ > - "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ > "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ > "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ > "tftpflash=tftpboot $loadaddr $uboot && " \ > -- > 1.8.5 > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
