Dear Eric Bénard,
In message <1395940250-2213-1-git-send-email-e...@eukrea.com> you wrote:
> this board is produced by Embest/Element 14 and is based on i.MX6 Solo
> The following features are tested :
....
You might use the clrbits / setbits / clrsetbits I/O accesses here:
> + /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
> + reg = readl(&mxc_ccm->CCGR3);
> + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
> + writel(reg, &mxc_ccm->CCGR3);
setbits_le32(&mxc_ccm->CCGR3,
MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK);
?
> + /* set LDB0, LDB1 clk select to 011/011 */
> + reg = readl(&mxc_ccm->cs2cdr);
> + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
> + | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
> + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
> + | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
> + writel(reg, &mxc_ccm->cs2cdr);
clrsetbits_le32(&mxc_ccm->cs2cdr,
MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK,
(3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET));
?
> + reg = readl(&mxc_ccm->cscmr2);
> + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
> + writel(reg, &mxc_ccm->cscmr2);
etc.
> +#define CONFIG_ARP_TIMEOUT 200UL
Do you need this on your boards?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
"Unibus timeout fatal trap program lost sorry" - An error message
printed by DEC's RSTS operating system for the PDP-11
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