Hi,
On 16.03.2014 11:42, armdev wrote:
Dear Michael,
Thanks for taking out time to extend help.
As per the RefManual the UART is taking the SCLK_UART Clock and as there are 4
channels (4 UARTS).
Following is from the public exynos 5250 manual
(http://www.samsung.com/global/business/semiconductor/file/product/Exynos_5_Dual_User_Manaul_Public_REV100-0.pdf)
"Four independent channels with asynchronous and serial input/output ports for
general purpose (Channel 0 to 3), and One channel in ISP (ISP-UART Channel 0)
…
• Each UART contains a Baud-rate generator, a Transmitter, a Receiver and a
Control Unit. The Baud-rate generator uses SCLK_UART."
Each UART block uses independent clock source, i.e. UART0 uses
SCLK_UART0 and UART3 uses SCLK_UART3.
Do you have MUX_UART3 and DIV_UART3 configured properly? Do you have the
IP bus clock (CLK_UART3) ungated?
The public manual contains full description of clock tree and clock
controller registers, so you should be able to figure this out.
Best regards,
Tomasz
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