From: David Feng <feng...@phytium.com.cn>
u-boot did not program the upper 32 bits of prefetchable base and limit
in pci bridge config space. I think it's needed when 64 bit address space
is used.
Changes for v1:
- use lowest bit of prefechable base(or limit) to determine whether
the bridge support 64 bit prefechable address space.
Signed-off-by: David Feng <feng...@phytium.com.cn>
---
drivers/pci/pci_auto.c | 38 ++++++++++++++++++++++++++++++++++++--
1 file changed, 36 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 86ba6b5..14652be 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -197,9 +197,12 @@ void pciauto_prescan_setup_bridge(struct pci_controller
*hose,
struct pci_region *pci_mem = hose->pci_mem;
struct pci_region *pci_prefetch = hose->pci_prefetch;
struct pci_region *pci_io = hose->pci_io;
- u16 cmdstat;
+ u16 cmdstat, prefechable_64;
pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
+ pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
+ &prefechable_64);
+ prefechable_64 &= 0x1;
/* Configure bus number registers */
pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
@@ -226,12 +229,26 @@ void pciauto_prescan_setup_bridge(struct pci_controller
*hose,
/* Set up memory and I/O filter limits, assume 32-bit I/O space
*/
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
(pci_prefetch->bus_lower & 0xfff00000)
>> 16);
+ if (prefechable_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+ pci_hose_write_config_dword(hose, dev,
+ PCI_PREF_BASE_UPPER32,
+ pci_prefetch->bus_lower >> 32);
+#else
+ pci_hose_write_config_dword(hose, dev,
+ PCI_PREF_BASE_UPPER32,
+ 0x0);
+#endif
cmdstat |= PCI_COMMAND_MEMORY;
} else {
/* We don't support prefetchable memory for now, so disable */
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
0x1000);
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
0x0);
+ if (prefechable_64) {
+ pci_hose_write_config_word(hose, dev,
PCI_PREF_BASE_UPPER32, 0x0);
+ pci_hose_write_config_word(hose, dev,
PCI_PREF_LIMIT_UPPER32, 0x0);
+ }
}
if (pci_io) {
@@ -271,11 +288,28 @@ void pciauto_postscan_setup_bridge(struct pci_controller
*hose,
}
if (pci_prefetch) {
+ u16 prefechable_64;
+
+ pci_hose_read_config_word(hose, dev,
+ PCI_PREF_MEMORY_LIMIT,
+ &prefechable_64);
+ prefechable_64 &= 0x1;
+
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_prefetch, 0x100000);
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
- (pci_prefetch->bus_lower - 1) >> 16);
+ (pci_prefetch->bus_lower - 1) >> 16);
+ if (prefechable_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+ pci_hose_write_config_dword(hose, dev,
+ PCI_PREF_LIMIT_UPPER32,
+ (pci_prefetch->bus_lower - 1) >> 32);
+#else
+ pci_hose_write_config_dword(hose, dev,
+ PCI_PREF_LIMIT_UPPER32,
+ 0x0);
+#endif
}
if (pci_io) {
--
1.7.9.5
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