-------- Original Message --------
Subject: [PATCH 2/3] armv8/cache: Flush D-cache, invalidate I-cache for
relocation
Date: Mon, 10 Feb 2014 13:55:53 -0800
From: York Sun <york...@freescale.com>
To: <albert.u.b...@aribaud.net>
CC: <scottw...@freescale.com>, York Sun <york...@freescale.com>, David Feng
<feng...@phytium.com.cn>
If D-cache is enabled, we need to flush it, and invalidate i-cache before
jumping to the new location. This should be done right after relocation.
Signed-off-by: York Sun <york...@freescale.com>
CC: David Feng <feng...@phytium.com.cn>
---
arch/arm/cpu/armv8/start.S | 6 ------
arch/arm/lib/relocate_64.S | 27 +++++++++++++++++++++++++++
2 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 90daa4d..e70c51d 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -122,12 +122,6 @@ ENDPROC(lowlevel_init)
/*-----------------------------------------------------------------------*/
ENTRY(c_runtime_cpu_setup)
- /* If I-cache is enabled invalidate it */
-#ifndef CONFIG_SYS_ICACHE_OFF
- ic iallu /* I+BTB cache invalidate */
- isb sy
-#endif
-
/* Relocate vBAR */
adr x0, vectors
switch_el x1, 3f, 2f, 1f
diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S
index 7fba9e2..3f36e88 100644
--- a/arch/arm/lib/relocate_64.S
+++ b/arch/arm/lib/relocate_64.S
@@ -19,6 +19,9 @@
* x0 holds the destination address.
*/
ENTRY(relocate_code)
+ stp x29, x30, [sp, #-32]! /* create a stack frame */
+ mov x29, sp
+ str x0, [sp, #16]
/*
* Copy u-boot from flash to RAM
*/
@@ -32,6 +35,7 @@ copy_loop:
stp x10, x11, [x0], #16 /* copy to target address [x0] */
cmp x1, x2 /* until source end address [x2] */
b.lo copy_loop
+ str x0, [sp, #24]
/*
* Fix .rela.dyn relocations
@@ -54,5 +58,28 @@ fixnext:
b.lo fixloop
relocate_done:
+ mrs x0, currentel
+ lsr w0, w0, #2
+ cmp w0, #0x3
+ b.ne 1f
+ mrs x0, sctlr_el3
+ b 4f
+1: cmp w0, #0x2
+ b.ne 2f
+ mrs x0, sctlr_el2
+ b 4f
+2: cmp w0, #0x1
+ b.ne 3f
+ mrs x0, sctlr_el1
+ b 4f
+3: bl hang
+4: tbz w0, #2, 4f /* flushing d-cache if enabled */
+ ldp x0, x1, [sp, #16]
+ bl __asm_flush_dcache_range
+#ifndef CONFIG_SYS_ICACHE_OFF
+ ic iallu /* I+BTB cache invalidate */
+ isb sy
+#endif
+4: ldp x29, x30, [sp],#16
ret
ENDPROC(relocate_code)
--
1.7.9.5
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