Detlev Zundel wrote: > Hi Jerry, > >> Detlev Zundel wrote: >>> Hello Shinya, >>> >>>> Detlev Zundel wrote: >>>>> As I said, I understand now why there were different data-types involved >>>>> although this was kind of non-obvious. So I take it, you had a working >>>>> configuration with REG_SIZE = 4, correct? >>>> I might be unclear. I used to use REG_SIZE = -16, as 16550 registers >>>> are located at 0, +0x10, +0x20, ..., . >> 16 byte stride. That is seriously odd. > > Isn't this "natural" for a 64-bitter?
Yes. I wasn't thinking of the processor as 64 bits. [snip] >> >> It sounds like Shinya has some pretty odd (read "broken") hardware >> that is decoding the registers with a 16 byte stride, although his >> example above shows a 4 byte stride (less broken). > > It's a 16-byte stride, although the register shows up neither at the > top, nor at the low end, but "slightly to the left", i.e. at offset 0x3 > ;) That is the big piece I didn't understand. Thanks and sorry for the noise. [snip] Best regards gvb _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
