On Wednesday 29 April 2009, Jean-Christophe PLAGNIOL-VILLARD wrote: > my idea is more this > the lowlovel will init the pll (lowlevel_init.S or other stage bootloader)
Right ... > so instead of hardcoding the PPLDIV read it in the register > and then calculate the clock rate That's all this code does: read the PLL registers (and divider taps), and display settings in use by the current board. It happens that some SoCs have slightly different PLL configuration (like pre/post dividers) and feed important components (ARM, DSP, DDR) from different PLL dividers. > and it need it set the other non used clock > depending on the IP used by u-boot (at runtime) I don't know what you mean here. PLL/tap configuration is distinct from clock distribution on the chip. The cpu/arm926ejs/davinci/psc.c code handles clock distribution (and resets). So for example the dm355 chips leave most modules clocked but in reset, while the dm6446 leaves them unclocked and in reset ... so modules needed by u-boot get uniformly taken out of reset and clocked. But that's *unrelated* to this PLL display code. - Dave _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
