Dear Aneesh Bansal, In message <1391419033-14283-1-git-send-email-aneesh.ban...@freescale.com> you wrote: > Changes: > 1. L2 cache is being invalidated by Boot ROM code for e6500 core. > So removing the invalidation from start.S > 2. Clear the LAW and corresponding configuration for CPC. Boot ROM > code uses it as hosekeeping area. > 3. For Secure boot, CPC is configured as SRAM and used as house > keeping area. This configuration is to be disabled once in uboot. > Earlier this disabling of CPC as SRAM was happening in cpu_init_r. > As a result cache invalidation function was getting skipped in > case CPC is configured as SRAM.This was causing random crashes. ... > +#if defined(CONFIG_RAMBOOT_PBL) > + disable_cpc_sram(); > +#endif
What is the meaning of this undocumented CONFIG_RAMBOOT_PBL option? As far as I understand, this is not a boot from RAM at all, but a totally normal step in a boot process form regular boot media? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de The perversity of nature is nowhere better demonstrated by the fact that, when exposed to the same atmosphere, bread becomes hard while crackers become soft. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
