These numbers will be reused by SPL.

Signed-off-by: Michal Simek <michal.si...@xilinx.com>
---

 arch/arm/include/asm/arch-zynq/hardware.h | 6 ++++++
 board/xilinx/zynq/board.c                 | 6 ------
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/arch-zynq/hardware.h 
b/arch/arm/include/asm/arch-zynq/hardware.h
index cd69677..1fe0448 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -21,6 +21,12 @@
 #define ZYNQ_SPI_BASEADDR1             0xE0007000
 #define ZYNQ_DDRC_BASEADDR             0xF8006000

+/* Bootmode setting values */
+#define ZYNQ_BM_MASK           0xF
+#define ZYNQ_BM_NOR            0x2
+#define ZYNQ_BM_SD             0x5
+#define ZYNQ_BM_JTAG           0x0
+
 /* Reflect slcr offsets */
 struct slcr_regs {
        u32 scl; /* 0x0 */
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 27aeaa4..82595fb 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -12,12 +12,6 @@

 DECLARE_GLOBAL_DATA_PTR;

-/* Bootmode setting values */
-#define ZYNQ_BM_MASK           0x0F
-#define ZYNQ_BM_NOR            0x02
-#define ZYNQ_BM_SD             0x05
-#define ZYNQ_BM_JTAG           0x0
-
 #ifdef CONFIG_FPGA
 Xilinx_desc fpga;

--
1.8.2.3

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