From: Jagannadha Sutradharudu Teki <jagannadha.sutradharudu-t...@xilinx.com>
This patch provides a basic fdt support for zynq u-boot.
zynq-generic.dts-> DTS for zc702
u-boot build: once configuring of a board done
for building dtb with zynq-zed.dts as an input
zynq-uboot> make DEVICE_TREE=zynq-zed
Signed-off-by: Jagannadha Sutradharudu Teki <jaga...@xilinx.com>
Signed-off-by: Michal Simek <michal.si...@xilinx.com>
---
Changes in v1: None
board/xilinx/dts/zynq-generic.dts | 421 ++++++++++++++++++++++++++++++++++++++
board/xilinx/zynq/board.c | 28 +--
include/configs/zynq.h | 21 +-
3 files changed, 437 insertions(+), 33 deletions(-)
create mode 100644 board/xilinx/dts/zynq-generic.dts
diff --git a/board/xilinx/dts/zynq-generic.dts
b/board/xilinx/dts/zynq-generic.dts
new file mode 100644
index 0000000..1524a6a
--- /dev/null
+++ b/board/xilinx/dts/zynq-generic.dts
@@ -0,0 +1,421 @@
+/*
+ * Device Tree Generator version: 1.1
+ *
+ * (C) Copyright 2007-2013 Xilinx, Inc.
+ * (C) Copyright 2007-2013 Michal Simek
+ * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
+ *
+ * Michal SIMEK <mon...@monstr.eu>
+ *
+ * CAUTION: This file is automatically generated by libgen.
+ * Version: Xilinx EDK 14.5 EDK_P.58f
+ *
+ */
+
+/dts-v1/;
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,zynq-7000";
+ model = "Xilinx Zynq";
+ aliases {
+ ethernet0 = &ps7_ethernet_0;
+ i2c0 = &ps7_i2c_0;
+ serial0 = &ps7_uart_1;
+ spi0 = &ps7_qspi_0;
+ } ;
+ chosen {
+ bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
+ linux,stdout-path = "/amba@0/serial@e0001000";
+ } ;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ps7_cortexa9_0: cpu@0 {
+ bus-handle = <&ps7_axi_interconnect_0>;
+ compatible = "arm,cortex-a9";
+ d-cache-line-size = <0x20>;
+ d-cache-size = <0x8000>;
+ device_type = "cpu";
+ i-cache-line-size = <0x20>;
+ i-cache-size = <0x8000>;
+ interrupt-handle = <&ps7_scugic_0>;
+ reg = <0x0>;
+ } ;
+ ps7_cortexa9_1: cpu@1 {
+ bus-handle = <&ps7_axi_interconnect_0>;
+ compatible = "arm,cortex-a9";
+ d-cache-line-size = <0x20>;
+ d-cache-size = <0x8000>;
+ device_type = "cpu";
+ i-cache-line-size = <0x20>;
+ i-cache-size = <0x8000>;
+ interrupt-handle = <&ps7_scugic_0>;
+ reg = <0x1>;
+ } ;
+ } ;
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupt-parent = <&ps7_scugic_0>;
+ interrupts = <0 5 4>, <0 6 4>;
+ reg = <0xf8891000 0x1000>, <0xf8893000 0x1000>;
+ reg-names = "cpu0", "cpu1";
+ } ;
+ ps7_ddr_0: memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ } ;
+ ps7_axi_interconnect_0: amba@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,ps7-axi-interconnect-1.00.a", "simple-bus";
+ ranges ;
+ ps7_afi_0: ps7-afi@f8008000 {
+ compatible = "xlnx,ps7-afi-1.00.a";
+ reg = <0xf8008000 0x1000>;
+ } ;
+ ps7_afi_1: ps7-afi@f8009000 {
+ compatible = "xlnx,ps7-afi-1.00.a";
+ reg = <0xf8009000 0x1000>;
+ } ;
+ ps7_afi_2: ps7-afi@f800a000 {
+ compatible = "xlnx,ps7-afi-1.00.a";
+ reg = <0xf800a000 0x1000>;
+ } ;
+ ps7_afi_3: ps7-afi@f800b000 {
+ compatible = "xlnx,ps7-afi-1.00.a";
+ reg = <0xf800b000 0x1000>;
+ } ;
+ ps7_can_0: ps7-can@e0008000 {
+ clock-names = "ref_clk", "aper_clk";
+ clocks = <&clkc 19>, <&clkc 36>;
+ compatible = "xlnx,ps7-can-1.00.a", "xlnx,ps7-can";
+ interrupt-parent = <&ps7_scugic_0>;
+ interrupts = <0 28 4>;
+ reg = <0xe0008000 0x1000>;
+ } ;
+ ps7_ddrc_0: ps7-ddrc@f8006000 {
+ compatible = "xlnx,ps7-ddrc-1.00.a", "xlnx,ps7-ddrc";
+ reg = <0xf8006000 0x1000>;
+ xlnx,has-ecc = <0x0>;
+ } ;
+ ps7_dev_cfg_0: ps7-dev-cfg@f8007000 {
+ clock-names = "ref_clk", "fclk0", "fclk1", "fclk2",
"fclk3";
+ clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc
17>, <&clkc 18>;
+ compatible = "xlnx,ps7-dev-cfg-1.00.a";
+ interrupt-parent = <&ps7_scugic_0>;
+ interrupts = <0 8 4>;
+ reg = <0xf8007000 0x100>;
+ } ;
+ ps7_dma_s: ps7-dma@f8003000 {
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <4>;
+ clock-names = "apb_pclk";
+ clocks = <&clkc 27>;
+ compatible = "xlnx,ps7-dma-1.00.a", "arm,primecell",
"arm,pl330";
+ interrupt-names = "abort", "dma0", "dma1", "dma2",
"dma3",
+ "dma4", "dma5", "dma6", "dma7";
+ interrupt-parent = <&ps7_scugic_0>;
+ interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0
17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>;
+ reg = <0xf8003000 0x1000>;
+ } ;
+ ps7_ethernet_0: ps7-ethernet@e000b000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "ref_clk", "aper_clk";
+ clocks = <&clkc 13>, <&clkc 30>;
+ compatible = "xlnx,ps7-ethernet-1.00.a";
+ enet-reset = <&ps7_gpio_0 11 0>;
+ interrupt-parent = <&ps7_scugic_0>;
+ interrupts = <0 22 4>;
+ local-mac-address = [00 0a 35 00 00 00];
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ reg = <0xe000b000 0x1000>;
+ xlnx,eth-mode = <0x1>;
+ xlnx,has-mdio = <0x1>;
+ xlnx,ptp-enet-clock = <111111115>;
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: phy@7 {
+ compatible = "marvell,88e1116r";
+ device_type = "ethernet-phy";
+ reg = <7>;
+ } ;
+ } ;
+ } ;
+ ps7_gpio_0: ps7-gpio@e000a000 {
+ #gpio-cells = <2>;
+ clocks = <&clkc 42>;
+ compatible = "xlnx,ps7-gpio-1.00.a";
+ emio-gpio-width = <64>;
+ gpio-controller ;
+ gpio-mask-high = <0x0>;
+ gpio-mask-low = <0x5600>;
+ interrupt-parent = <&ps7_scugic_0>;
+ interrupts = <0 20 4>;
+ reg = <0xe000a000 0x1000>;
+ } ;
+ ps7_i2c_0: ps7-i2c@e0004000 {
+ bus-id = <0>;
+ clocks = <&clkc 38>;
+ compatible = "xlnx,ps7-i2c-1.00.a";
+ i2c-clk = <400000>;
+ i2c-reset = <&ps7_gpio_0 13 0>;
+ interrupt-parent = <&ps7_scugic_0>;
+ interrupts = <0 25 4>;
+ reg = <0xe0004000 0x1000>;
+ xlnx,has-interrupt = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2cswitch@74 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ si570: clock-generator@5d {
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ temperature-stability = <50>;
+ reg = <0x5d>;
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ };
+ };
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ eeprom@54 {
+ compatible = "at,24c08";
+ reg = <0x54>;
+ };
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ gpio@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ rtc@54 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+ };
+
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ hwmon@52 {
+ compatible = "pmbus,ucd9248";
+ reg = <52>;
+ };
+ hwmon@53 {
+ compatible = "pmbus,ucd9248";
+ reg = <53>;
+ };
+ hwmon@54 {
+ compatible = "pmbus,ucd9248";
+ reg = <54>;
+ };
+ };
+ };
+
+ } ;
+ ps7_iop_bus_config_0: ps7-iop-bus-config@e0200000 {
+ compatible = "xlnx,ps7-iop-bus-config-1.00.a";
+ reg = <0xe0200000 0x1000>;
+ } ;
+ ps7_ocmc_0: ps7-ocmc@f800c000 {
+ compatible = "xlnx,ps7-ocmc-1.00.a",
"xlnx,zynq-ocm-1.0";
+ interrupt-parent = <&ps7_scugic_0>;
+ interrupts = <0 3 4>;
+ reg = <0xf800c000 0x1000>;
+ } ;
+ ps7_pl310_0: ps7-pl310@f8f02000 {
+ arm,data-latency = <3 2 2>;
+ arm,tag-latency = <2 2 2>;
+ cache-level = <2>;
+ cache-unified ;
+ compatible = "xlnx,ps7-pl310-1.00.a", "arm,pl310-cache";
+ interrupt-parent = <&ps7_scugic_0>;
+ interrupts = <0 2 4>;
+ reg = <0xf8f02000 0x1000>;
+ } ;
+ ps7_qspi_0: ps7-qspi@e000d000 {
+ clock-names = "ref_clk", "aper_clk";
+ clocks = <&clkc 10>, <&clkc 43>;
+ compatible = "xlnx,ps7-qspi-1.00.a";
+ interrupt-parent = <&ps7_scugic_0>;
+ interrupts = <0 19 4>;
+ is-dual = <0>;
+ num-chip-select = <1>;
+ reg = <0xe000d000 0x1000>;
+ xlnx,fb-clk = <0x1>;
+ xlnx,qspi-mode = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ flash@0 {
+ compatible = "n25q128";
+ reg = <0x0>;
+ spi-max-frequency = <50000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@qspi-fsbl-uboot {
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@qspi-linux {
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@qspi-device-tree {
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@qspi-rootfs {
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5E0000>;
+ };
+ partition@qspi-bitstream {
+ label = "qspi-bitstream";
+ reg = <0xC00000 0x400000>;
+ };
+ };
+
+ } ;
+ ps7_qspi_linear_0: ps7-qspi-linear@fc000000 {
+ clock-names = "ref_clk", "aper_clk";
+ clocks = <&clkc 10>, <&clkc 43>;
+ compatible = "xlnx,ps7-qspi-linear-1.00.a";
+ reg = <0xfc000000 0x1000000>;
+ } ;
+ ps7_scugic_0: ps7-scugic@f8f01000 {
+ #address-cells = <2>;
+ #interrupt-cells = <3>;
+ #size-cells = <1>;
+ compatible = "xlnx,ps7-scugic-1.00.a",
"arm,cortex-a9-gic", "arm,gic";
+ interrupt-controller ;
+ num_cpus = <2>;
+ num_interrupts = <96>;
+ reg = <0xf8f01000 0x1000>, <0xf8f00100 0x100>;
+ } ;
+ ps7_scutimer_0: ps7-scutimer@f8f00600 {
+ clocks = <&clkc 4>;
+ compatible = "xlnx,ps7-scutimer-1.00.a",
"arm,cortex-a9-twd-timer";
+ interrupt-parent = <&ps7_scugic_0>;
+ interrupts = <1 13 0x301>;
+ reg = <0xf8f00600 0x20>;
+ } ;
+ ps7_scuwdt_0: ps7-scuwdt@f8f00620 {
+ clocks = <&clkc 4>;
+ compatible = "xlnx,ps7-scuwdt-1.00.a";
+ device_type = "watchdog";
+ interrupt-parent = <&ps7_scugic_0>;
+ interrupts = <1 14 0x301>;
+ reg = <0xf8f00620 0xe0>;
+ } ;
+ ps7_sd_0: ps7-sdio@e0100000 {
+ clock-frequency = <50000000>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clkc 21>, <&clkc 32>;
+ compatible = "xlnx,ps7-sdio-1.00.a", "generic-sdhci",
"arasan,sdhci-8.9a";
+ interrupt-parent = <&ps7_scugic_0>;
+ interrupts = <0 24 4>;
+ reg = <0xe0100000 0x1000>;
+ xlnx,has-cd = <0x1>;
+ xlnx,has-power = <0x0>;
+ xlnx,has-wp = <0x1>;
+ } ;
+ ps7_slcr_0: ps7-slcr@f8000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,ps7-slcr-1.00.a", "xlnx,zynq-slcr",
"syscon";
+ reg = <0xf8000000 0x1000>;
+ clkc: clkc@100 {
+ #clock-cells = <1>;
+ clock-output-names = "armpll", "ddrpll",
"iopll", "cpu_6or4x", "cpu_3or2x",
+ "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
"dci",
+ "lqspi", "smc", "pcap", "gem0", "gem1",
+ "fclk0", "fclk1", "fclk2", "fclk3",
"can0",
+ "can1", "sdio0", "sdio1", "uart0",
"uart1",
+ "spi0", "spi1", "dma", "usb0_aper",
"usb1_aper",
+ "gem0_aper", "gem1_aper", "sdio0_aper",
"sdio1_aper", "spi0_aper",
+ "spi1_aper", "can0_aper", "can1_aper",
"i2c0_aper", "i2c1_aper",
+ "uart0_aper", "uart1_aper",
"gpio_aper", "lqspi_aper", "smc_aper",
+ "swdt", "dbg_trc", "dbg_apb";
+ compatible = "xlnx,ps7-clkc";
+ fclk-enable = <0xf>;
+ ps-clk-frequency = <33333333>;
+ reg = <0x100 0x100>;
+ } ;
+ } ;
+ ps7_ttc_0: ps7-ttc@f8001000 {
+ clocks = <&clkc 6>;
+ compatible = "xlnx,ps7-ttc-1.00.a", "cdns,ttc";
+ interrupt-names = "ttc0", "ttc1", "ttc2";
+ interrupt-parent = <&ps7_scugic_0>;
+ interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
+ reg = <0xf8001000 0x1000>;
+ } ;
+ ps7_uart_1: serial@e0001000 {
+ clock-names = "ref_clk", "aper_clk";
+ clocks = <&clkc 24>, <&clkc 41>;
+ compatible = "xlnx,ps7-uart-1.00.a", "xlnx,xuartps";
+ current-speed = <115200>;
+ device_type = "serial";
+ interrupt-parent = <&ps7_scugic_0>;
+ interrupts = <0 50 4>;
+ port-number = <0>;
+ reg = <0xe0001000 0x1000>;
+ xlnx,has-modem = <0x0>;
+ } ;
+ ps7_usb_0: ps7-usb@e0002000 {
+ clocks = <&clkc 28>;
+ compatible = "xlnx,ps7-usb-1.00.a";
+ dr_mode = "host";
+ interrupt-parent = <&ps7_scugic_0>;
+ interrupts = <0 21 4>;
+ phy_type = "ulpi";
+ reg = <0xe0002000 0x1000>;
+ usb-reset = <&ps7_gpio_0 7 0>;
+ } ;
+ ps7_wdt_0: ps7-wdt@f8005000 {
+ clocks = <&clkc 45>;
+ compatible = "xlnx,ps7-wdt-1.00.a";
+ device_type = "watchdog";
+ interrupt-parent = <&ps7_scugic_0>;
+ interrupts = <0 9 1>;
+ reg = <0xf8005000 0x1000>;
+ reset = <0>;
+ timeout = <10>;
+ } ;
+ ps7_xadc: ps7-xadc@f8007100 {
+ clocks = <&clkc 12>;
+ compatible = "xlnx,ps7-xadc-1.00.a";
+ interrupt-parent = <&ps7_scugic_0>;
+ interrupts = <0 7 4>;
+ reg = <0xf8007100 0x20>;
+ } ;
+ } ;
+} ;
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 6629b20..139e48c 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -95,28 +95,13 @@ int board_eth_init(bd_t *bis)
ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
XILINX_AXIDMA_BASEADDR);
#endif
+
#ifdef CONFIG_XILINX_EMACLITE
- u32 txpp = 0;
- u32 rxpp = 0;
-# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
- txpp = 1;
-# endif
-# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
- rxpp = 1;
-# endif
- ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
- txpp, rxpp);
+ xilinx_emaclite_of_init(gd->fdt_blob);
#endif
#if defined(CONFIG_ZYNQ_GEM)
-# if defined(CONFIG_ZYNQ_GEM0)
- ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
- CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
-# endif
-# if defined(CONFIG_ZYNQ_GEM1)
- ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
- CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
-# endif
+ zynq_gem_of_init(gd->fdt_blob);
#endif
return ret;
}
@@ -128,12 +113,7 @@ int board_mmc_init(bd_t *bd)
int ret = 0;
#if defined(CONFIG_ZYNQ_SDHCI)
-# if defined(CONFIG_ZYNQ_SDHCI0)
- ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
-# endif
-# if defined(CONFIG_ZYNQ_SDHCI1)
- ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
-# endif
+ ret = zynq_sdhci_of_init(gd->fdt_blob);
#endif
return ret;
}
diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index 5e7adc2..b21e060 100644
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
@@ -37,16 +37,14 @@
# define CONFIG_ARM_DCC
# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
#else
-# define CONFIG_ZYNQ_SERIAL_BASEADDR1
# define CONFIG_ZYNQ_SERIAL
#endif
+#define CONFIG_ZYNQ_GEM
+
/* Ethernet driver */
-#define CONFIG_ZYNQ_GEM0
-#define CONFIG_ZYNQ_GEM_PHY_ADDR0 7
-#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1)
+#ifdef CONFIG_ZYNQ_GEM
# define CONFIG_NET_MULTI
-# define CONFIG_ZYNQ_GEM
# define CONFIG_MII
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_PHYLIB
@@ -64,13 +62,13 @@
/* NOR */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_SDHCI
+
/* MMC */
-#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
+#if defined(CONFIG_ZYNQ_SDHCI)
# define CONFIG_MMC
# define CONFIG_GENERIC_MMC
# define CONFIG_SDHCI
-# define CONFIG_ZYNQ_SDHCI
# define CONFIG_CMD_MMC
# define CONFIG_CMD_FAT
# define CONFIG_SUPPORT_VFAT
@@ -165,7 +163,6 @@
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0
-#define CONFIG_SYS_SDRAM_SIZE 0x40000000
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
@@ -190,6 +187,12 @@
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
+/* FDT support */
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_EMBED
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_DEFAULT_DEVICE_TREE "zynq-generic"
+
/* Boot FreeBSD/vxWorks from an ELF image */
#if defined(CONFIG_ZYNQ_BOOT_FREEBSD)
# define CONFIG_API
--
1.8.2.3
pgpg5GX_AEdkG.pgp
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