Hi Rajeshwari,
On 16 December 2013 01:42, Rajeshwari S Shinde <rajeshwar...@samsung.com> wrote:
> This patch intends to add DDR3 initialization code for Exynos5420.
>
> Signed-off-by: Akshay Saraswat <aksha...@samsung.com>
> Signed-off-by: Rajeshwari S Shinde <rajeshwar...@samsung.com>
> ---
> Changes in V2:
> - Corrected a compilation issue for SMDK5250.
> Changes in V3:
> - None
> Changes in V4:
> - None
> Changes in V5:
> - None
> Changes in V6:
> - None
> Changes in V7:
> - Fixed multi line comment.
> Changes in V8:
> - None
> Changes in V9:
> - Used samsung_get base to get the dmc base address
> Changes in V10:
> - Changed to new 5420 dmc and power resgister structure.
> - Changed the input parameters for dmc common functions
> due to changes in the dmc register structure.
> Changes in V11:
> - None
> arch/arm/cpu/armv7/exynos/dmc_common.c | 60 ++--
> arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 439
> +++++++++++++++++++++++++++++-
> arch/arm/cpu/armv7/exynos/exynos5_setup.h | 26 +-
> arch/arm/include/asm/arch-exynos/cpu.h | 7 +-
> arch/arm/include/asm/arch-exynos/dmc.h | 10 +
> 5 files changed, 484 insertions(+), 58 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/dmc_common.c
> b/arch/arm/cpu/armv7/exynos/dmc_common.c
> index 53cfe6e..520eac5 100644
> --- a/arch/arm/cpu/armv7/exynos/dmc_common.c
> +++ b/arch/arm/cpu/armv7/exynos/dmc_common.c
> @@ -1,5 +1,5 @@
> /*
> - * Mem setup common file for different types of DDR present on SMDK5250
> boards.
> + * Mem setup common file for different types of DDR present on Exynos boards.
> *
> * Copyright (C) 2012 Samsung Electronics
> *
> @@ -15,9 +15,9 @@
>
> #define ZQ_INIT_TIMEOUT 10000
>
> -int dmc_config_zq(struct mem_timings *mem,
> - struct exynos5_phy_control *phy0_ctrl,
> - struct exynos5_phy_control *phy1_ctrl)
> +int dmc_config_zq(struct mem_timings *mem, const void *phy0_con16,
> + const void *phy1_con16, const void *phy0_con17,
> + const void *phy1_con17)
Could these be uint32_t * or similar? Also, why const? It looks like
you are writing to them.
> {
> unsigned long val = 0;
> int i;
> @@ -31,19 +31,19 @@ int dmc_config_zq(struct mem_timings *mem,
> val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT;
> val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT;
> val |= ZQ_CLK_DIV_EN;
> - writel(val, &phy0_ctrl->phy_con16);
> - writel(val, &phy1_ctrl->phy_con16);
> + writel(val, phy0_con16);
> + writel(val, phy1_con16);
>
> /* Disable termination */
> if (mem->zq_mode_noterm)
> val |= PHY_CON16_ZQ_MODE_NOTERM_MASK;
> - writel(val, &phy0_ctrl->phy_con16);
> - writel(val, &phy1_ctrl->phy_con16);
> + writel(val, phy0_con16);
> + writel(val, phy1_con16);
>
Regards,
Simon
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