On Fri, 2013-12-13 at 21:09 -0600, Liu Po-B43644 wrote: > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: Saturday, December 14, 2013 4:26 AM > > To: Liu Po-B43644 > > Cc: u-boot@lists.denx.de; Sun York-R58495; Kushwaha Prabhakar-B32579 > > Subject: Re: [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND boot > > support base on TPL/SPL > > > > On Wed, 2013-12-11 at 00:16 -0600, Liu Po-B43644 wrote: > > > > > SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, > > CONFIG_SYS_NAND_BASE_PHYS, > > > > > - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > > > > > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > > > > > 0, 5, BOOKE_PAGESZ_64K, 1), > > > > > > > > No. > > > Without MAS3_SX, the board can't run in booting from NAND. > > > > Explain why you're executing from this TLB entry. This should be for > > accessing the NAND as I/O after you've relocated away from the boot > > buffer. There should be a different mapping for the boot buffer early on. > > None of the other NAND boot targets have needed this. Perhaps this is > > related to the other TLB entry that you said you could work without. > This is because for SPL, the > #define CONFIG_SPL_TEXT_BASE 0xff800000 > #define CONFIG_SYS_NAND_BASE 0xff800000 > Code space overlap the nand io space.
OK, I guess we move the NAND buffer before relocating out of it. And for some reason I missed that existing targets do the same thing. Never mind... -Scott _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
