This file declares many address spaces for ar7240 System On Chip Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasalou...@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierz...@gmail.com> --- arch/mips/include/asm/ar7240_addrspace.h | 387 +++++++++++++++++++++++++++++++ 1 file changed, 387 insertions(+) create mode 100644 arch/mips/include/asm/ar7240_addrspace.h
diff --git a/arch/mips/include/asm/ar7240_addrspace.h b/arch/mips/include/asm/ar7240_addrspace.h new file mode 100644 index 0000000..4da8f63 --- /dev/null +++ b/arch/mips/include/asm/ar7240_addrspace.h @@ -0,0 +1,387 @@ +/* + * Atheror AR7240 series processor SOC registers + * + * Copyright (C) 2008 Atheros Communications, Inc. + * + * Copyright (C) 2013 Imagination Technologies + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _AR7240_SOC_H +#define _AR7240_SOC_H + +/* + * Address map + */ +#define AR7240_PCI_MEM_BASE 0x10000000 /* 128M */ +#define AR7240_APB_BASE 0x18000000 /* 384M */ +#define AR7240_GE0_BASE 0x19000000 /* 16M */ +#define AR7240_GE1_BASE 0x1a000000 /* 16M */ +#define AR7240_USB_EHCI_BASE 0x1b000000 +#define AR7240_USB_OHCI_BASE 0x1c000000 +#define AR7240_SPI_BASE 0x1f000000 +#define ATH_NAND_FLASH_BASE 0x1b000000u + +/* + * APB block + */ +#define AR7240_DDR_CTL_BASE AR7240_APB_BASE+0x00000000 +#define AR7240_CPU_BASE AR7240_APB_BASE+0x00010000 +#define AR7240_UART_BASE AR7240_APB_BASE+0x00020000 +#define AR7240_USB_CONFIG_BASE AR7240_APB_BASE+0x00030000 +#define AR7240_GPIO_BASE AR7240_APB_BASE+0x00040000 +#define AR7240_PLL_BASE AR7240_APB_BASE+0x00050000 +#define AR7240_RESET_BASE AR7240_APB_BASE+0x00060000 +#define AR7240_ETH_BASE AR7240_APB_BASE+0x00070000 +#define AR7240_PCI_BASE AR7240_APB_BASE+0x000c0000 +#define AR7240_PCI_RC_BASE AR7240_APB_BASE+0x000f0000 +#define AR7240_BASEBAND_SRIF_REGS AR7240_APB_BASE+0x00116180 +#define AR7240_CPU_SRIF_REGS AR7240_APB_BASE+0x001161c0 +#define AR7240_DDR_SRIF_REGS AR7240_APB_BASE+0x00116240 +#define AR7240_PCIE_SRIF_REGS AR7240_APB_BASE+0x00116c00 + +#if !defined(__ASSEMBLY__) +/* + * DDR block + */ +struct ar_ddr { + u32 config; + u32 config2; + u32 mode; + u32 ext_mode; + u32 ctrl; + u32 refresh; + u32 rd_data_this_cycle; + u32 tap_ctrl0; + u32 tap_ctrl1; + u32 tap_ctrl2; + u32 tap_ctrl3; +}; + +struct ar_ddr2 { + u32 config; + u32 ext_mode2; + u32 ext_mode3; + u32 burst; + u32 burst2; + u32 ahb_master_timeout_max; +}; + +struct ar_ddr_ctl { + u32 config; + u32 self_refresh; + u32 self_refresh_timer; + u32 debug_read_ctrl; +}; + +/* + * PCIE FIFO flushes + */ +struct ar_flush { + u32 ddr_wb_gmac0; + u32 ddr_wb_gmac1; + u32 ddr_wb_usb; + u32 ddr_wb_pcie; + u32 ddr_wb_wmac; +}; + +/* + * USB block + */ +#define AR7240_USB_FLADJ_VAL AR7240_USB_CONFIG_BASE +#define AR7240_USB_CONFIG AR7240_USB_CONFIG_BASE+0x4 +#define AR7240_USB_WINDOW 0x1000000 + +/* + * gpio configs + */ +struct ar_gpio { + u32 oe; + u32 in; + u32 out; + u32 set; + u32 clear; + u32 int_en; + u32 int_type; + u32 int_polarity; + u32 int_pending; + u32 int_mask; +}; + +#define AR7240_GPIO_COUNT 16 + +/* + * PLL + */ +struct ar_pll { + u32 cpu_config; + u32 ddr_config; + u32 cpu_ddr_clk_ctrl; + u32 cpu_sync; + u32 pcie_config; + u32 pcie_dither_div_max; + u32 pcie_dither_div_min; + u32 pcie_dither_step; + u32 ldo_power_ctrl; + u32 switch_clk_spare; + u32 current_pcie_dither; + u32 eth_xmii_config; + u32 audio_config; + u32 audio_modulation; + u32 audio_mod_step; + u32 current_audio_modulation; + u32 bb_config; + u32 ddr_dither; + u32 cpu_dither; +}; + +#define PLL_CONFIG_PLL_DIV_MASK (0x3ff << 0) +#define PLL_CONFIG_PLL_REF_DIV_MASK (0xf << 10) +#define PLL_CONFIG_PLL_BYPASS_MASK (0x1 << 16) +#define PLL_CONFIG_PLL_UPDATE_MASK (0x1 << 17) +#define PLL_CONFIG_PLL_NOPWD_MASK (0x1 << 18) +#define PLL_CONFIG_AHB_DIV_MASK (0x1 << 19) +#define PLL_CONFIG_DDR_DIV_MASK (0x1 << 22) +#define PLL_CONFIG_PLL_RESET_MASK (0x1 << 25) + +#define CLOCK_CONTROL_CLOCK_SWITCH_MASK (1 << 0) +#define CLOCK_CONTROL_RST_SWITCH_MASK (1 << 1) + +/* + * Reset block + */ +struct ar_reset1 { + u32 general_tmr1; + u32 general_tmr1_reload; + u32 watchdog_tmr_ctrl; + u32 watchdog_tmr; + u32 misc_interrupt_status; + u32 misc_interrupt_mask; + u32 global_interrupt_status; + u32 reset; +}; + +struct ar_reset2 { + u32 rev_id; + u32 general_tmr2; + u32 general_tmr2_reload; + u32 general_tmr3; + u32 general_tmr3_reload; + u32 general_tmr4; + u32 general_tmr4_reload; + u32 pcie_wmac_interrupt_status; + u32 bootstrap; + u32 spare_sticky; + u32 misc2; +}; + +/* + * RESET bit defines + */ +#define AR7240_RESET_EXTERNAL (1 << 28) +#define AR7240_RESET_WMAC (1 << 27) +#define AR7240_RESET_FULL_CHIP (1 << 24) +#define AR7240_RESET_CPU_NMI (1 << 21) +#define AR7240_RESET_CPU_COLD_RESET_MASK (1 << 20) +#define AR7240_RESET_DDR (1 << 16) +#define AR7240_RESET_GE1_MAC (1 << 13) +#define AR7240_RESET_GE1_MDIO (1 << 23) +#define AR7240_RESET_GE1_PHY (1 << 12) /* Not valid */ +#define AR7240_RESET_PCIE_PHY_SERIAL (1 << 10) +#define AR7240_RESET_GE0_MAC (1 << 9) +#define AR7240_RESET_GE0_MDIO (1 << 22) +#define AR7240_RESET_GE0_PHY (1 << 8) /* Switch reset */ +#define AR7240_RESET_PCIE_PHY (1 << 7) +#define AR7240_RESET_PCIE (1 << 6) +#define AR7240_RESET_USB_HOST (1 << 5) +#define AR7240_RESET_USB_OHCI_DLL (1 << 3) + +/* + * Ethernet config registers + */ +#define AR7240_ETH_CFG AR7240_ETH_BASE+0 +#define AR7240_ETH_CFG_RGMII_GE0 (1<<0) +#define AR7240_ETH_CFG_MII_GE0 (1<<1) +#define AR7240_ETH_CFG_GMII_GE0 (1<<2) +#define AR7240_ETH_CFG_RMII_GE0 (1<<10) +#define AR7240_ETH_CFG_RMII_HISPD_GE0 (1<<11) +#define AR7240_ETH_CFG_RMII_MASTER_MODE (1<<12) +#define AR7240_ETH_CFG_MII_GE0_MASTER (1<<3) +#define AR7240_ETH_CFG_MII_GE0_SLAVE (1<<4) +#define AR7240_ETH_CFG_GE0_ERR_EN (1<<5) +#define AR7240_ETH_CFG_SW_ONLY_MODE (1<<6) +#define AR7240_ETH_CFG_SW_PHY_SWAP (1<<7) +#define AR7240_ETH_CFG_SW_PHY_ADDR_SWAP (1<<8) +#define AR7240_ETH_CFG_RXD_DELAY (1 << 14) +#define AR7240_ETH_CFG_RDV_DELAY (1 << 16) + +#define AR7240_PCI_RESET AR7240_PCI_RC_BASE+0x18 + +/* + * PCI DPLL + */ +struct ar_pci_rc_phy { + u32 dpll1; + u32 dpll2; + u32 dpll3; +}; + +#define AR7240_PMU1 AR7240_PCIE_SRIF_REGS+0x40 +#define AR7240_PMU2 AR7240_PCIE_SRIF_REGS+0x44 + +/* + * SPI Flash + */ +struct ar_spi { + u32 function_select; + u32 control; + u32 io_control; + u32 read_data; + u32 shift_dataout; + u32 shift_count; + u32 shift_datain; +}; + +#define AR7240_SPI_CTRL_RELOCATE (1 << 7) +#define AR7240_SPI_CTRL_REMAP_DISABLE (1 << 6) +#define AR7240_SPI_CTRL_CLK_DIV(x) ((x) & 0x3f) + +extern const struct ar_ddr *ar7240_ddr; +extern const struct ar_ddr2 *ar7240_ddr2; +extern const struct ar_ddr_ctl *ar7240_ddr_ctl; +extern const struct ar_flush *ar7240_flush; +extern const struct ar_gpio *ar7240_gpio; +extern const struct ar_pll *ar7240_pll; +extern const struct ar_reset1 *ar7240_rst1; +extern const struct ar_reset2 *ar7240_rst2; +extern const struct ar_pci_rc_phy *ar7240_pci_rc; +extern const struct ar_spi *ar7240_spi; + +#else /* defined __ASSEMBLY__ */ +#define ATH_DDR_COUNT_LOC 0xbd000000 +#define ATH_CPU_COUNT_LOC 0xbd000004 + +#define AR934X_CPU_PLL_CONFIG AR7240_PLL_BASE+0x0000 +#define AR934X_DDR_PLL_CONFIG AR7240_PLL_BASE+0x0004 +#define AR934X_CPU_DDR_CLOCK_CONTROL AR7240_PLL_BASE+0x0008 +#define AR934X_DDR_PLL_DITHER AR7240_PLL_BASE+0x0044 +#define AR934X_CPU_PLL_DITHER AR7240_PLL_BASE+0x0048 +#define WASP_BOOTSTRAP_REG AR7240_RESET_BASE+0xb0 + +#define CPU_DPLL1_ADDRESS AR7240_CPU_SRIF_REGS +#define CPU_DPLL2_ADDRESS AR7240_CPU_SRIF_REGS+0x4 +#define CPU_DPLL3_ADDRESS AR7240_CPU_SRIF_REGS+0x8 +#define DDR_DPLL1_ADDRESS AR7240_DDR_SRIF_REGS +#define DDR_DPLL2_ADDRESS AR7240_DDR_SRIF_REGS+0x4 +#define DDR_DPLL3_ADDRESS AR7240_DDR_SRIF_REGS+0x8 +#define DDR_DPLL4_ADDRESS AR7240_DDR_SRIF_REGS+0xc +#define BASEBAND_DPLL3_ADDRESS AR7240_BASEBAND_SRIF_REGS+0x8 + +#endif /* END __ASSEMBLY__ */ + +/* + * PLL config for different CPU/DDR/AHB frequencies + */ +#define UBOOT_SIZE (256 * 1024) +#define PLL_FLASH_ADDR (CONFIG_SYS_FLASH_BASE + UBOOT_SIZE) +#define PLL_CONFIG_VAL_F \ + (PLL_FLASH_ADDR + CONFIG_SYS_FLASH_SECTOR_SIZE - 0x20) +#define PLL_MAGIC 0xaabbccdd +#define SRIF_PLL_CONFIG_VAL_F (PLL_CONFIG_VAL_F - 12) +#define SRIF_PLL_MAGIC 0x73726966 /* srif */ + +#define XTAL_ADDRESS 0x18116290 + +/* + * REV_IDs similar to AR7240 + */ +#define AR7240_REV_ID_MASK 0xffff +#define AR9344_REV_ID_MASK 0xfff0 /* Ignore minor id */ + +#define AR7240_REV_ID_AR7130 0xa0 +#define AR7240_REV_ID_AR7141 0xa1 +#define AR7240_REV_ID_AR7161 0xa2 +#define AR7240_REV_1_0 0xc0 +#define AR7240_REV_1_1 0xc1 +#define AR7240_REV_1_2 0xc2 +#define AR7241_REV_1_0 0x0100 +#define AR7242_REV_1_0 0x1100 +#define AR7241_REV_1_1 0x0101 +#define AR7242_REV_1_1 0x1101 + +#define AR9330_REV_1_0 0x0110 /* 5-port:0x110,4-port 0x1110 */ +#define AR9331_REV_1_0 0x1110 +#define AR9330_REV_1_1 0x0111 /* 5-port:0x111,4-port 0x1111 */ +#define AR9331_REV_1_1 0x1111 +#define AR9330_REV_1_2 0x0112 +#define AR9331_REV_1_2 0x1112 + +#define AR9344_REV_1_x 0x2120 /* Wasp 1.x, ignore minor id */ +#define AR9342_REV_1_x 0x1120 +#define AR9341_REV_1_x 0x0120 + +#define AR9344_REV_1_0 0x2120 /* Wasp 1.0 */ +#define AR9342_REV_1_0 0x1120 +#define AR9341_REV_1_0 0x0120 + +#define AR9344_REV_1_1 0x2121 /* Wasp 1.1 */ +#define AR9342_REV_1_1 0x1121 +#define AR9341_REV_1_1 0x0121 + +#define is_ar7240(rst2) \ + (((ar_reg_rd(rst2->rev_id) & AR7240_REV_ID_MASK) == AR7240_REV_1_2) || \ + ((ar_reg_rd(rst2->rev_id) & AR7240_REV_ID_MASK) == AR7240_REV_1_1) ||\ + ((ar_reg_rd(rst2->rev_id) & AR7240_REV_ID_MASK) == AR7240_REV_1_0)) + +#define is_ar7241(rst2) \ + (((ar_reg_rd(rst2->rev_id) & AR7240_REV_ID_MASK) == AR7241_REV_1_0) ||\ + ((ar_reg_rd(rst2->rev_id) & AR7240_REV_ID_MASK) == AR7241_REV_1_1)) + +#define is_ar7242(rst2) \ + (((ar_reg_rd(rst2->rev_id) & AR7240_REV_ID_MASK) == AR7242_REV_1_0) ||\ + ((ar_reg_rd(rst2->rev_id) & AR7240_REV_ID_MASK) == AR7242_REV_1_1)) + +#define is_ar9330(rst2) \ + (((ar_reg_rd(rst2->rev_id) & AR7240_REV_ID_MASK) == AR9330_REV_1_0) ||\ + ((ar_reg_rd(rst2->rev_id) & AR7240_REV_ID_MASK) == AR9330_REV_1_1) ||\ + ((ar_reg_rd(rst2->rev_id) & AR7240_REV_ID_MASK) == AR9330_REV_1_2)) + +#define is_ar9331(rst2) \ + (((ar_reg_rd(rst2->rev_id) & AR7240_REV_ID_MASK) == AR9331_REV_1_0) ||\ + ((ar_reg_rd(rst2->rev_id) & AR7240_REV_ID_MASK) == AR9331_REV_1_1) ||\ + ((ar_reg_rd(rst2->rev_id) & AR7240_REV_ID_MASK) == AR9331_REV_1_2)) + +#define is_ar933x_10(rst2) \ + (((ar_reg_rd(rst2->rev_id) & AR7240_REV_ID_MASK) == AR9330_REV_1_0) ||\ + ((ar_reg_rd(rst2->rev_id) & AR7240_REV_ID_MASK) == AR9331_REV_1_0)) + +#define is_ar933x_11(rst2) \ + (((ar_reg_rd(rst2->rev_id) & AR7240_REV_ID_MASK) == AR9330_REV_1_1) ||\ + ((ar_reg_rd(rst2->rev_id) & AR7240_REV_ID_MASK) == AR9331_REV_1_1)) + +#define is_ar933x_12(rst2) \ + (((ar_reg_rd(rst2->rev_id) & AR7240_REV_ID_MASK) == AR9330_REV_1_2) ||\ + ((ar_reg_rd(rst2->rev_id) & AR7240_REV_ID_MASK) == AR9331_REV_1_2)) + +#define is_ar9344(rst2) \ + ((ar_reg_rd(rst2->rev_id) & AR9344_REV_ID_MASK) == AR9344_REV_1_x) +#define is_ar9342(rst2) \ + ((ar_reg_rd(rst2->rev_id) & AR9344_REV_ID_MASK) == AR9342_REV_1_x) +#define is_ar9341(rst2) \ + ((ar_reg_rd(rst2->rev_id) & AR9344_REV_ID_MASK) == AR9341_REV_1_x) + +#define is_ar933x(rst2) (is_ar9330(rst2) || is_ar9331(rst2)) +#define is_ar934x(rst2) (is_ar9341(rst2) || is_ar9342(rst2) || \ + is_ar9344(rst2)) + +#define ar_reg_rd(_addr) readl(KSEG1ADDR((_addr))) +#define ar_reg_wr(_addr, _val) writel((_val), KSEG1ADDR((_addr))) + +#define ar_reg_rd_set(_reg, _mask) \ + ar_reg_wr((_reg), (ar_reg_rd((_reg)) | (_mask))) + +#define ar_reg_rd_clr(_reg, _mask) \ + ar_reg_wr((_reg), (ar_reg_rd((_reg)) & ~(_mask))) + +#endif -- 1.8.3.2 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot