The DRAM base has been zero for Power SoCs. It could be non-zero
for ARM SoCs. Use a macro instead of hard-coding to zero.
Signed-off-by: York Sun <york...@freescale.com>
---
Change log
v4: rebase to latset master
v3: no change
v2: no change since v1
drivers/ddr/fsl/main.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index b4988e1..d0cd589 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -255,7 +255,7 @@ static unsigned long long
__step_assign_addresses(fsl_ddr_info_t *pinfo,
debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
}
- current_mem_base = 0ull;
+ current_mem_base = CONFIG_SYS_DDR_SDRAM_BASE;
total_mem = 0;
if (pinfo->memctl_opts[0].memctl_interleaving) {
rank_density = pinfo->dimm_params[0][0].rank_density >>
@@ -535,8 +535,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int
start_step,
}
}
- total_mem = 1 + (((unsigned long long)max_end << 24ULL)
- | 0xFFFFFFULL);
+ total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
+ 0xFFFFFFULL) - CONFIG_SYS_DDR_SDRAM_BASE;
}
return total_mem;
--
1.7.9.5
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