Hi, Dependency of below patch marked under --- [U-Boot] powerpc/t1040qds: Add DDR Raw Timing support http://patchwork.ozlabs.org/patch/286112/ no longer holds true as thi patch has been deferred.
But below emulator patch will work as it is with SPD method. No changes required. Regards Priyanka > -----Original Message----- > From: Jain Priyanka-B32167 > Sent: Monday, October 28, 2013 3:53 PM > To: u-boot@lists.denx.de; w...@denx.de > Cc: sun york-R58495; Jain Priyanka-B32167; Aggrwal Poonam-B10812; > Kushwaha Prabhakar-B32579 > Subject: [PATCH][v2] powerpc/T1040EMU: Add T1040 emulator support > > Add emulator support for T1040. Emulator has limited peripherals and > interfaces. > Difference between T1040QDS and emulator includes: > -ECC for DDR is disabled due to procedure to load images -Depends on raw > timing for DDR initialization -No board FPGA (Qixis) -No PCI -No SPI -No > flash support > > Signed-off-by: Poonam Aggrwal <poonam.aggr...@freescale.com> > Signed-off-by: Prabhakar Kushwaha <prabha...@freescale.com> > Signed-off-by: Priyanka Jain <priyanka.j...@freescale.com> > --- > Changes for v2: Incorporated Wolfgang Denk's review comments > > Based on u-boot-mpc85xx/next branch. > This patch depends upon following patches: > 1)[U-Boot] powerpc/t1040qds: Add DDR Raw Timing support > http://patchwork.ozlabs.org/patch/286112/ > 2)[U-Boot] powerpc/t1040qds: Correct Maintainer name in boards.cfg > http://patchwork.ozlabs.org/patch/286113/ > > board/freescale/t1040qds/Makefile | 3 +- > board/freescale/t1040qds/ddr.c | 3 + > board/freescale/t1040qds/ddr.h | 13 ++ > board/freescale/t1040qds/t1040emu.c | 75 ++++++++ > board/freescale/t1040qds/tlb.c | 4 + > boards.cfg | 1 + > include/configs/T1040EMU.h | 344 > +++++++++++++++++++++++++++++++++++ > 7 files changed, 442 insertions(+), 1 deletions(-) create mode 100644 > board/freescale/t1040qds/t1040emu.c > create mode 100644 include/configs/T1040EMU.h > > diff --git a/board/freescale/t1040qds/Makefile > b/board/freescale/t1040qds/Makefile > index 8f0057b..4bd7103 100644 > --- a/board/freescale/t1040qds/Makefile > +++ b/board/freescale/t1040qds/Makefile > @@ -8,7 +8,8 @@ include $(TOPDIR)/config.mk > > LIB = $(obj)lib$(BOARD).o > > -COBJS-y += $(BOARD).o > +COBJS-$(CONFIG_T1040QDS) += t1040qds.o > +COBJS-$(CONFIG_T1040EMU) += t1040emu.o > COBJS-y += ddr.o > COBJS-$(CONFIG_PCI) += pci.o > COBJS-y += law.o > diff --git a/board/freescale/t1040qds/ddr.c > b/board/freescale/t1040qds/ddr.c index 16ab829..d46021b 100644 > --- a/board/freescale/t1040qds/ddr.c > +++ b/board/freescale/t1040qds/ddr.c > @@ -123,6 +123,9 @@ phys_size_t initdram(int board_type) > puts("Initializing....using SPD\n"); > > dram_size = fsl_ddr_sdram(); > +#ifdef CONFIG_T1040EMU > + dram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; #endif > > dram_size = setup_ddr_tlbs(dram_size / 0x100000); > dram_size *= 0x100000; > diff --git a/board/freescale/t1040qds/ddr.h > b/board/freescale/t1040qds/ddr.h index 4a4f76a..5e0a078 100644 > --- a/board/freescale/t1040qds/ddr.h > +++ b/board/freescale/t1040qds/ddr.h > @@ -54,6 +54,18 @@ struct board_specific_parameters { > * for each n_ranks group. > */ > > +#ifdef CONFIG_T1040EMU > +static const struct board_specific_parameters udimm0[] = { > + /* > + * memory controller 0 > + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo > |wrdata|2T > + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay > | > + */ > + {2, 2140, 4, 4, 8, 0x0, 0x0, 0xff, 2, 0}, > + {1, 2140, 4, 4, 8, 0x0, 0x0, 0xff, 2, 0}, > + {} > +}; > +#else > static const struct board_specific_parameters udimm0[] = { > /* > * memory controller 0 > @@ -72,6 +84,7 @@ static const struct board_specific_parameters udimm0[] > = { > {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, > {} > }; > +#endif > > static const struct board_specific_parameters *udimms[] = { > udimm0, > diff --git a/board/freescale/t1040qds/t1040emu.c > b/board/freescale/t1040qds/t1040emu.c > new file mode 100644 > index 0000000..e9362d6 > --- /dev/null > +++ b/board/freescale/t1040qds/t1040emu.c > @@ -0,0 +1,75 @@ > +/* > + * Copyright 2013 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <command.h> > +#include <i2c.h> > +#include <netdev.h> > +#include <linux/compiler.h> > +#include <asm/mmu.h> > +#include <asm/processor.h> > +#include <asm/cache.h> > +#include <asm/immap_85xx.h> > +#include <asm/fsl_law.h> > +#include <asm/fsl_serdes.h> > +#include <asm/fsl_portals.h> > +#include <asm/fsl_liodn.h> > +#include <fm_eth.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +int checkboard(void) > +{ > + struct cpu_type *cpu = gd->arch.cpu; > + printf("Board: %sEMU\n", cpu->name); > + return 0; > +} > + > +int board_early_init_r(void) > +{ > + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; > + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); > + > + /* > + * Remap Boot flash + PROMJET region to caching-inhibited > + * so that flash can be erased properly. > + */ > + > + /* Flush d-cache and invalidate i-cache of any FLASH data */ > + flush_dcache(); > + invalidate_icache(); > + > + /* invalidate existing TLB entry for flash + promjet */ > + disable_tlb(flash_esel); > + > + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, > + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > + 0, flash_esel, BOOKE_PAGESZ_256M, 1); > + set_liodns(); > +#ifdef CONFIG_SYS_DPAA_QBMAN > + setup_portals(); > +#endif > + > + return 0; > +} > + > + > +int misc_init_r(void) > +{ > + return 0; > +} > + > +void ft_board_setup(void *blob, bd_t *bd) { > + phys_addr_t base; > + phys_size_t size; > + > + ft_cpu_setup(blob, bd); > + base = getenv_bootm_low(); > + size = getenv_bootm_size(); > + fdt_fixup_memory(blob, (u64)base, (u64)size); > + fdt_fixup_liodn(blob); > +} > diff --git a/board/freescale/t1040qds/tlb.c > b/board/freescale/t1040qds/tlb.c index 412c591..0bc3960 100644 > --- a/board/freescale/t1040qds/tlb.c > +++ b/board/freescale/t1040qds/tlb.c > @@ -53,15 +53,19 @@ struct fsl_e_tlb_entry tlb_table[] = { > MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, > 0, 2, BOOKE_PAGESZ_256M, 1), > > +#ifdef CONFIG_SYS_PCIE1_MEM_PHYS > /* *I*G* - PCI */ > SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, > CONFIG_SYS_PCIE1_MEM_PHYS, > MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > 0, 3, BOOKE_PAGESZ_1G, 1), > +#endif > > +#ifdef CONFIG_SYS_PCIE1_IO_PHYS > /* *I*G* - PCI I/O */ > SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, > CONFIG_SYS_PCIE1_IO_PHYS, > MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, > 0, 4, BOOKE_PAGESZ_256K, 1), > +#endif > > /* Bman/Qman */ > #ifdef CONFIG_SYS_BMAN_MEM_PHYS > diff --git a/boards.cfg b/boards.cfg > index dfe1c59..11efdd4 100644 > --- a/boards.cfg > +++ b/boards.cfg > @@ -962,6 +962,7 @@ Active powerpc mpc85xx - > freescale t4qds > Active powerpc mpc85xx - freescale t4qds > T4240QDS_SDCARD > T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 > - > Active powerpc mpc85xx - freescale t4qds > T4240QDS_SPIFLASH > T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 > - > Active powerpc mpc85xx - freescale t4qds > T4240QDS_SRIO_PCIE_BOOT > T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 > - > +Active powerpc mpc85xx - freescale t1040qds > T1040EMU T1040EMU:PPC_T1040 > Poonam Aggrwal <poonam.aggr...@freescale.com> > Active powerpc mpc85xx - freescale t1040qds > T1040QDS T1040QDS:PPC_T1040 > Poonam Aggrwal <poonam.aggr...@freescale.com> > Active powerpc mpc85xx - gdsys p1022 > controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD > Dirk Eibach <eib...@gdsys.de> > Active powerpc mpc85xx - gdsys p1022 > controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP > Dirk Eibach <eib...@gdsys.de> > diff --git a/include/configs/T1040EMU.h b/include/configs/T1040EMU.h new > file mode 100644 index 0000000..8c547f2 > --- /dev/null > +++ b/include/configs/T1040EMU.h > @@ -0,0 +1,344 @@ > +/* > + * Copyright 2013 Freescale Semiconductor, Inc. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +/* > + * T1040 Emulator configuration file > + */ > +#define CONFIG_T1040EMU > +#define CONFIG_PHYS_64BIT > + > +#ifdef CONFIG_RAMBOOT_PBL > +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE > +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc > +#endif > + > +/* High Level Configuration Options */ > +#define CONFIG_BOOKE > +#define CONFIG_E500 /* BOOKE e500 family */ > +#define CONFIG_E500MC /* BOOKE e500mc family */ > +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ > +#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ > +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ > +#define CONFIG_MP /* support multiple processors */ > +#define CONFIG_SYS_NO_FLASH 1 > +#define CONFIG_SYS_FSL_DDR_EMU 1 > +#define CONFIG_SYS_FSL_NO_QIXIS 1 > +#define CONFIG_SYS_FSL_NO_SERDES 1 > + > +#ifndef CONFIG_SYS_TEXT_BASE > +#define CONFIG_SYS_TEXT_BASE 0xeff80000 > +#endif > + > +#ifndef CONFIG_RESET_VECTOR_ADDRESS > +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc > +#endif > + > +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ > +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS > +#define CONFIG_FSL_IFC /* Enable IFC Support */ > + > +#define CONFIG_FSL_LAW /* Use common FSL init code */ > + > +#define CONFIG_ENV_OVERWRITE > + > +#ifdef CONFIG_SYS_NO_FLASH > +#define CONFIG_ENV_IS_NOWHERE > +#else > +#define CONFIG_FLASH_CFI_DRIVER > +#define CONFIG_SYS_FLASH_CFI > +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #endif #define > +CONFIG_ENV_IS_NOWHERE > +#define CONFIG_ENV_SIZE 0x2000 > +#ifndef __ASSEMBLY__ > +unsigned long get_board_sys_clk(void); > +unsigned long get_board_ddr_clk(void); > +#endif > + > +#define CONFIG_SYS_CLK_FREQ 100000000 > +#define CONFIG_DDR_CLK_FREQ 100000000 > + > +/* > + * These can be toggled for performance analysis, otherwise use default. > + */ > +#define CONFIG_SYS_CACHE_STASHING > +#define CONFIG_BACKSIDE_L2_CACHE > +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E > +#define CONFIG_BTB /* toggle branch predition */ > +#ifdef CONFIG_DDR_ECC > +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER > +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef > +#endif > + > +#define CONFIG_ENABLE_36BIT_PHYS > + > +#define CONFIG_ADDR_MAP > +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 > entries > */ > + > +#define CONFIG_PANIC_HANG /* do not reset board on panic */ > + > +/* > + * Config the L3 Cache as L3 SRAM > + */ > +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE > + > +#define CONFIG_SYS_DCSRBAR 0xf0000000 > +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull > + > +/* > + * DDR Setup > + */ > +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 > +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE > + > +/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h > */ > +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 > +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * > CONFIG_DIMM_SLOTS_PER_CTLR) > + > +#define CONFIG_DDR_SPD > +#define CONFIG_SYS_DDR_RAW_TIMING > +#define CONFIG_FSL_DDR3 > + > +#define CONFIG_SYS_SPD_BUS_NUM 0 > +#define SPD_EEPROM_ADDRESS 0x51 > + > +#define CONFIG_SYS_SDRAM_SIZE 1024 /* for fixed parameter use */ > + > +/* > + * IFC Definitions > + */ > +#define CONFIG_SYS_FLASH_BASE 0xe0000000 > +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | > +CONFIG_SYS_FLASH_BASE) > + > +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) > +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS > \ > + + 0x8000000) | \ > + CSPR_PORT_SIZE_16 | \ > + CSPR_MSEL_NOR | \ > + CSPR_V) > +#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) > +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) > | \ > + CSPR_PORT_SIZE_16 | \ > + CSPR_MSEL_NOR | \ > + CSPR_V) > +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) > +/* NOR Flash Timing Params */ > +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(0) > +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ > + FTIM0_NOR_TEADC(0x1) | \ > + FTIM0_NOR_TEAHC(0x1)) > +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ > + FTIM1_NOR_TRAD_NOR(0x1)) > +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ > + FTIM2_NOR_TCH(0x0) | \ > + FTIM2_NOR_TWP(0x1)) > +#define CONFIG_SYS_NOR_FTIM3 0x04000000 > +#define CONFIG_SYS_IFC_CCR 0x01000000 > + > +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT > +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR > +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK > +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR > +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 > +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 > +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 > +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 > + > +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE > + > +#if defined(CONFIG_RAMBOOT_PBL) > +#define CONFIG_SYS_RAMBOOT > +#endif > + > +#define CONFIG_BOARD_EARLY_INIT_R > +#define CONFIG_MISC_INIT_R > + > +#define CONFIG_HWCONFIG > + > +/* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM > +#define CONFIG_SYS_INIT_RAM_LOCK > +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ > +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf > +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 > +/* The assembler doesn't like typecast */ #define > +CONFIG_SYS_INIT_RAM_ADDR_PHYS \ > + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ > + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) > +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 > + > +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ > + GENERATED_GBL_DATA_SIZE) > +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET > + > +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) > +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) > + > +/* > + * Serial Port > + * open - index 2 > + * shorted - index 1 > + */ > +#define CONFIG_CONS_INDEX 1 > +#define CONFIG_SYS_NS16550 > +#define CONFIG_SYS_NS16550_SERIAL > +#define CONFIG_SYS_NS16550_REG_SIZE 1 > +#define CONFIG_SYS_NS16550_CLK 300000000 > + > +#define CONFIG_SYS_BAUDRATE_TABLE \ > + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} > + > +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) > +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) > +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) > +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) > +#define CONFIG_SERIAL_MULTI /* Enable both serial ports */ > +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment > */ > + > +/* Use the HUSH parser */ > +#define CONFIG_SYS_HUSH_PARSER > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " > + > +/* pass open firmware flat tree */ > +#define CONFIG_OF_LIBFDT > +#define CONFIG_OF_BOARD_SETUP > +#define CONFIG_OF_STDOUT_VIA_ALIAS > + > +/* FIT support */ > +#define CONFIG_FIT > +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ > + > +/* I2C support */ > +#define CONFIG_SYS_I2C > +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ > +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ > +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F > +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ > +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F > +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 > +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 > + > +/* Qman/Bman */ > +#ifndef CONFIG_NOBQFMAN > +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ > +#define CONFIG_SYS_BMAN_NUM_PORTALS 25 > +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 > +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull > +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 > +#define CONFIG_SYS_QMAN_NUM_PORTALS 25 > +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 > +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull > +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 > + > +#define CONFIG_SYS_DPAA_FMAN > +#define CONFIG_SYS_DPAA_PME > + > +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR > +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 > +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 > +#define CONFIG_SYS_FDT_PAD (0x3000 + > CONFIG_SYS_QE_FMAN_FW_LENGTH) > +#endif > + > +/* > + * Environment > + */ > +#define CONFIG_LOADS_ECHO /* echo on for serial download */ > +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ > + > +/* > + * Command line configuration. > + */ > +#include <config_cmd_default.h> > + > +#define CONFIG_CMD_IRQ > +#define CONFIG_CMD_I2C > + > +/* > + * Miscellaneous configurable options > + */ > +#define CONFIG_SYS_LONGHELP /* undef to save memory */ > +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ > +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ > +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ > +#ifdef CONFIG_CMD_KGDB > +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ > +#else > +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ > +#endif > +#define CONFIG_SYS_PBSIZE > (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) > +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer > Size */ > +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ > + > +/* > + * For booting Linux, the board info and command line data > + * have to be in the first 64 MB of memory, since this is > + * the maximum mapped by the Linux kernel during initialization. > + */ > +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ > +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ > + > +#ifdef CONFIG_CMD_KGDB > +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial > port */ > +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ > +#endif > + > +/* > + * Environment Configuration > + */ > +#define CONFIG_ROOTPATH "/opt/nfsroot" > +#define CONFIG_BOOTFILE "uImage" > +#define CONFIG_UBOOTPATH "u-boot.bin"/* U-Boot image on TFTP > server*/ > + > +/* default location for tftp and bootm */ > +#define CONFIG_LOADADDR 1000000 > + > +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ > + > +#define CONFIG_BAUDRATE 14745600 > + > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ > + "bank_intlv=cs0_cs1;\0" \ > + "netdev=eth0\0" \ > + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ > + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ > + "consoledev=ttyS0\0" \ > + "ramdiskaddr=2000000\0" \ > + "ramdiskfile=t1040emu/ramdisk.uboot\0" \ > + "fdtaddr=c00000\0" \ > + "fdtfile=t1040emu/t1040emu.dtb\0" \ > + "bdev=sda3\0" > +/* > + * For emulation this causes u-boot to jump to the start of the proof > +point > + * app code automatically > + */ > +#define CONFIG_PROOF_POINTS \ > + "setenv bootargs root=/dev/$bdev rw " \ > + "console=$consoledev,$baudrate $othbootargs;" \ > + "cpu 1 release 0x29000000 - - -;" \ > + "cpu 2 release 0x29000000 - - -;" \ > + "cpu 3 release 0x29000000 - - -;" \ > + "cpu 4 release 0x29000000 - - -;" \ > + "cpu 5 release 0x29000000 - - -;" \ > + "cpu 6 release 0x29000000 - - -;" \ > + "cpu 7 release 0x29000000 - - -;" \ > + "go 0x29000000\0" > + > +#define CONFIG_LINUX \ > + "setenv bootargs root=/dev/ram rw " \ > + "console=$consoledev,$baudrate $othbootargs;" \ > + "setenv ramdiskaddr 0x02000000;" \ > + "setenv fdtaddr 0x00c00000;" \ > + "setenv loadaddr 0x1000000;" \ > + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" > + > +#define CONFIG_BOOTCOMMAND CONFIG_LINUX > + > +#endif /* __CONFIG_H */ > -- > 1.7.4.1 > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de 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