On Tue, Apr 21, 2009 at 05:38:21PM +0200, Dirk Behme wrote:
> Ladislav Michl wrote:
>> On Mon, Apr 20, 2009 at 08:27:34PM +0200, Dirk Behme wrote:
>>> Just to get an idea of the math:
>>>
>>> CONFIG_SYS_CLK_FREQ is 12000000 (12MHz)? This is divided by 256, so
>>> TIMER_CLOCK is 46875Hz? A free running 32-bit count down timer is
>>> used starting at 0xffffffff? Underflow (0) is reached after ~91626s
>>> == ~25hours with this?
>>>
>>> Please correct if something is wrong ;)
>>
>> Math is perfectly correct, except in my case CONFIG_SYS_CLK_FREQ is 150MHz,
>> so resolution is actually 12.5 times better.
>
> Ok. Is this 150MHz defined in one of the configs you modify with this
> patch or do you use a custom config? Just curious ;)
All three 32-bit counters receive a dedicated clock from clock generator
module 1 (either CLKIN or DPLL1 output). You will find CONFIG_SYS_CLK_FREQ
defined to be 150000000 in include/configs/netstar.h and code in
board/netstar/setup.S selects DPLL1 as a clock source (and you'll probably
notice that netstar's lowlevel_init code looks different from all others just
because it was not copied, but written from scratch long before its author
even explored u-boot's existence, so take care when copying anything from
netstar's config file as it handles low level init different way).
>> Perhaps I should modify those
>> boards wich uses 12MHz clock to use smaller divisor,
>
> Yes, this should be easily doable by changing CONFIG_SYS_PTV.
Yes, I'll send updated patch.
[snip]
>> Right, but the key point here is to unbind udelay from get_timer as now
>> get_timer works with miliseconds resolution.
>
> I hope I got it right with the updated patch sent some minutes ago.
Yes, that one looks definitely better (although I have no way to test it).
ladis
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