1) Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using
software leveling. This was done since hardware leveling was not
working. Now that the right sequence to do hw leveling is identified,
use it. This is required for EMIF clockdomain to idle and come back
during lowpower usecases
2) When core power domain hits oswr, then DDR3 memories does not come back
while resuming. This is because when EMIF registers are lost, then the
controller takes care of copying the values from the shadow registers.
If the shadow registers are not updated with the right values, then this
results in incorrect settings while resuming. So updating the shadow
registers
with the corresponding status registers here during the boot.
Sricharan R (3):
ARM: DRA7: Add is_dra7xx cpu check definition
ARM: DRA: EMIF: Change DDR3 settings to use hw leveling
ARM: DRA7/OMAP5: EMIF: Add workaround for bug 0039
arch/arm/cpu/armv7/omap-common/emif-common.c | 142 +++++++++++++----
arch/arm/cpu/armv7/omap5/hw_data.c | 9 +-
arch/arm/cpu/armv7/omap5/hwinit.c | 12 +-
arch/arm/cpu/armv7/omap5/sdram.c | 214 ++++++++++++++++++--------
arch/arm/include/asm/arch-omap5/omap.h | 1 +
arch/arm/include/asm/emif.h | 14 +-
arch/arm/include/asm/omap_common.h | 8 +
7 files changed, 301 insertions(+), 99 deletions(-)
--
1.7.9.5
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