Hi Stefan, On Tue, 24 Sep 2013 08:22:19 +0200, Stefan Roese <s...@denx.de> wrote:
> Remove Prodrive pdnb3 board (including the scpu variant) support > from mainline. As its unmaintained and not needed any more for > quite some time. > > Signed-off-by: Stefan Roese <s...@denx.de> > Cc: Martijn de Gouw <martijn.de.g...@prodrive.nl> > Cc: Albert Aribaud <albert.u.b...@aribaud.net> > --- > v2: > - Rebased on current master > - Added entries for pdnb3 and scpu to doc/README.scrapyard > > board/prodrive/pdnb3/Makefile | 28 ---- > board/prodrive/pdnb3/flash.c | 73 ---------- > board/prodrive/pdnb3/nand.c | 129 ----------------- > board/prodrive/pdnb3/pdnb3.c | 220 ----------------------------- > boards.cfg | 2 - > doc/README.scrapyard | 2 + > include/configs/pdnb3.h | 322 > ------------------------------------------ > 7 files changed, 2 insertions(+), 774 deletions(-) > delete mode 100644 board/prodrive/pdnb3/Makefile > delete mode 100644 board/prodrive/pdnb3/flash.c > delete mode 100644 board/prodrive/pdnb3/nand.c > delete mode 100644 board/prodrive/pdnb3/pdnb3.c > delete mode 100644 include/configs/pdnb3.h > > diff --git a/board/prodrive/pdnb3/Makefile b/board/prodrive/pdnb3/Makefile > deleted file mode 100644 > index 5e4a909..0000000 > --- a/board/prodrive/pdnb3/Makefile > +++ /dev/null > @@ -1,28 +0,0 @@ > -# > -# (C) Copyright 2006 > -# Wolfgang Denk, DENX Software Engineering, w...@denx.de. > -# > -# SPDX-License-Identifier: GPL-2.0+ > -# > - > -include $(TOPDIR)/config.mk > - > -LIB = $(obj)lib$(BOARD).o > - > -COBJS := flash.o pdnb3.o nand.o > - > -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) > -OBJS := $(addprefix $(obj),$(COBJS)) > -SOBJS := $(addprefix $(obj),$(SOBJS)) > - > -$(LIB): $(obj).depend $(OBJS) > - $(call cmd_link_o_target, $(OBJS)) > - > -######################################################################### > - > -# defines $(obj).depend target > -include $(SRCTREE)/rules.mk > - > -sinclude $(obj).depend > - > -######################################################################### > diff --git a/board/prodrive/pdnb3/flash.c b/board/prodrive/pdnb3/flash.c > deleted file mode 100644 > index 75b5d05..0000000 > --- a/board/prodrive/pdnb3/flash.c > +++ /dev/null > @@ -1,73 +0,0 @@ > -/* > - * (C) Copyright 2006 > - * Stefan Roese, DENX Software Engineering, s...@denx.de. > - * > - * SPDX-License-Identifier: GPL-2.0+ > - */ > - > -#include <common.h> > -#include <asm/arch/ixp425.h> > - > -#if !defined(CONFIG_FLASH_CFI_DRIVER) > - > -/* > - * include common flash code (for esd boards) > - */ > -#include "../common/flash.c" > - > -/* > - * Prototypes > - */ > -static ulong flash_get_size (vu_long * addr, flash_info_t * info); > - > -static inline ulong ld(ulong x) > -{ > - ulong k = 0; > - > - while (x >>= 1) > - ++k; > - > - return k; > -} > - > -unsigned long flash_init(void) > -{ > - unsigned long size; > - int i; > - > - /* Init: no FLASHes known */ > - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; i++) > - flash_info[i].flash_id = FLASH_UNKNOWN; > - > - size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); > - > - if (flash_info[0].flash_id == FLASH_UNKNOWN) > - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld > MB\n", > - size, size<<20); > - > - /* Reconfigure CS0 to actual FLASH size */ > - *IXP425_EXP_CS0 = (*IXP425_EXP_CS0 & ~0x00003C00) | ((ld(size) - 9) << > 10); > - > - /* Monitor protection ON by default */ > - flash_protect(FLAG_PROTECT_SET, > - CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + > monitor_flash_len - 1, > - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); > - > - /* Environment protection ON by default */ > - flash_protect(FLAG_PROTECT_SET, > - CONFIG_ENV_ADDR, > - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, > - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); > - > - /* Redundant environment protection ON by default */ > - flash_protect(FLAG_PROTECT_SET, > - CONFIG_ENV_ADDR_REDUND, > - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, > - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); > - > - flash_info[0].size = size; > - > - return size; > -} > - > -#endif /* CONFIG_FLASH_CFI_DRIVER */ > diff --git a/board/prodrive/pdnb3/nand.c b/board/prodrive/pdnb3/nand.c > deleted file mode 100644 > index e1d2c63..0000000 > --- a/board/prodrive/pdnb3/nand.c > +++ /dev/null > @@ -1,129 +0,0 @@ > -/* > - * (C) Copyright 2006 > - * Stefan Roese, DENX Software Engineering, s...@denx.de. > - * > - * SPDX-License-Identifier: GPL-2.0+ > - */ > - > -#include <common.h> > - > -#if defined(CONFIG_CMD_NAND) > - > -#include <nand.h> > - > -struct pdnb3_ndfc_regs { > - uchar cmd; > - uchar wait; > - uchar addr; > - uchar term; > - uchar data; > -}; > - > -static u8 hwctl; > -static struct pdnb3_ndfc_regs *pdnb3_ndfc; > - > -#define readb(addr) *(volatile u_char *)(addr) > -#define readl(addr) *(volatile u_long *)(addr) > -#define writeb(d,addr) *(volatile u_char *)(addr) = (d) > - > -/* > - * The PDNB3 has a NAND Flash Controller (NDFC) that handles all accesses to > - * the NAND devices. The NDFC has command, address and data registers that > - * when accessed will set up the NAND flash pins appropriately. We'll use > the > - * hwcontrol function to save the configuration in a global variable. > - * We can then use this information in the read and write functions to > - * determine which NDFC register to access. > - * > - * There is one NAND devices on the board, a Hynix HY27US08561A (32 MByte). > - */ > -static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int > ctrl) > -{ > - struct nand_chip *this = mtd->priv; > - > - if (ctrl & NAND_CTRL_CHANGE) { > - if ( ctrl & NAND_CLE ) > - hwctl |= 0x1; > - else > - hwctl &= ~0x1; > - if ( ctrl & NAND_ALE ) > - hwctl |= 0x2; > - else > - hwctl &= ~0x2; > - if ( (ctrl & NAND_NCE) != NAND_NCE) > - writeb(0x00, &(pdnb3_ndfc->term)); > - } > - if (cmd != NAND_CMD_NONE) > - writeb(cmd, this->IO_ADDR_W); > -} > - > - > -static u_char pdnb3_nand_read_byte(struct mtd_info *mtd) > -{ > - return readb(&(pdnb3_ndfc->data)); > -} > - > -static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, > int len) > -{ > - int i; > - > - for (i = 0; i < len; i++) { > - if (hwctl & 0x1) > - writeb(buf[i], &(pdnb3_ndfc->cmd)); > - else if (hwctl & 0x2) > - writeb(buf[i], &(pdnb3_ndfc->addr)); > - else > - writeb(buf[i], &(pdnb3_ndfc->data)); > - } > -} > - > -static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) > -{ > - int i; > - > - for (i = 0; i < len; i++) > - buf[i] = readb(&(pdnb3_ndfc->data)); > -} > - > -static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, > int len) > -{ > - int i; > - > - for (i = 0; i < len; i++) > - if (buf[i] != readb(&(pdnb3_ndfc->data))) > - return i; > - > - return 0; > -} > - > -static int pdnb3_nand_dev_ready(struct mtd_info *mtd) > -{ > - /* > - * Blocking read to wait for NAND to be ready > - */ > - readb(&(pdnb3_ndfc->wait)); > - > - /* > - * Return always true > - */ > - return 1; > -} > - > -int board_nand_init(struct nand_chip *nand) > -{ > - pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CONFIG_SYS_NAND_BASE; > - > - nand->ecc.mode = NAND_ECC_SOFT; > - > - /* Set address of NAND IO lines (Using Linear Data Access Region) */ > - nand->IO_ADDR_R = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4); > - nand->IO_ADDR_W = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4); > - /* Reference hardware control function */ > - nand->cmd_ctrl = pdnb3_nand_hwcontrol; > - nand->read_byte = pdnb3_nand_read_byte; > - nand->write_buf = pdnb3_nand_write_buf; > - nand->read_buf = pdnb3_nand_read_buf; > - nand->verify_buf = pdnb3_nand_verify_buf; > - nand->dev_ready = pdnb3_nand_dev_ready; > - return 0; > -} > -#endif > diff --git a/board/prodrive/pdnb3/pdnb3.c b/board/prodrive/pdnb3/pdnb3.c > deleted file mode 100644 > index fa320da..0000000 > --- a/board/prodrive/pdnb3/pdnb3.c > +++ /dev/null > @@ -1,220 +0,0 @@ > -/* > - * (C) Copyright 2006 > - * Stefan Roese, DENX Software Engineering, s...@denx.de. > - * > - * SPDX-License-Identifier: GPL-2.0+ > - */ > - > -#include <common.h> > -#include <command.h> > -#include <malloc.h> > -#include <asm/arch/ixp425.h> > - > -DECLARE_GLOBAL_DATA_PTR; > - > -/* predefine these here for FPGA programming (before including fpga.c) */ > -#define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data) > -#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE) > -#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT) > -#define OLD_VAL old_val > - > -static unsigned long old_val = 0; > - > -/* > - * include common fpga code (for prodrive boards) > - */ > -#include "../common/fpga.c" > - > -/* > - * Miscelaneous platform dependent initialisations > - */ > -int board_init(void) > -{ > - /* adress of boot parameters */ > - gd->bd->bi_boot_params = 0x00000100; > - > - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET); > - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET); > - > - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING); > - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING); > - > - /* > - * Setup GPIO's for FPGA programming > - */ > - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG); > - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK); > - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA); > - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG); > - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK); > - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA); > - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT); > - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE); > - > - /* > - * Setup GPIO's for interrupts > - */ > - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA); > - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA); > - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB); > - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB); > - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT); > - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT); > - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT); > - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT); > - > - /* > - * Setup GPIO's for 33MHz clock output > - */ > - *IXP425_GPIO_GPCLKR = 0x01FF0000; > - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M); > - > - /* > - * Setup other chip select's > - */ > - *IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1; > - > - return 0; > -} > - > -/* > - * Check Board Identity > - */ > -int checkboard(void) > -{ > - char buf[64]; > - int i = getenv_f("serial#", buf, sizeof(buf)); > - > - puts("Board: PDNB3"); > - > - if (i > 0) { > - puts(", serial# "); > - puts(buf); > - } > - putc('\n'); > - > - return (0); > -} > - > -int dram_init(void) > -{ > - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; > - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; > - > - return (0); > -} > - > -int do_fpga_boot(unsigned char *fpgadata) > -{ > - unsigned char *dst; > - int status; > - int index; > - int i; > - ulong len = CONFIG_SYS_MALLOC_LEN; > - > - /* > - * Setup GPIO's for FPGA programming > - */ > - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG); > - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK); > - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA); > - > - /* > - * Save value so no readback is required upon programming > - */ > - old_val = *IXP425_GPIO_GPOUTR; > - > - /* > - * First try to decompress fpga image (gzip compressed?) > - */ > - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); > - if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != > 0) { > - printf("Error: Image has to be gzipp'ed!\n"); > - return -1; > - } > - > - status = fpga_boot(dst, len); > - if (status != 0) { > - printf("\nFPGA: Booting failed "); > - switch (status) { > - case ERROR_FPGA_PRG_INIT_LOW: > - printf("(Timeout: INIT not low after asserting > PROGRAM*)\n "); > - break; > - case ERROR_FPGA_PRG_INIT_HIGH: > - printf("(Timeout: INIT not high after deasserting > PROGRAM*)\n "); > - break; > - case ERROR_FPGA_PRG_DONE: > - printf("(Timeout: DONE not high after programming > FPGA)\n "); > - break; > - } > - > - /* display infos on fpgaimage */ > - index = 15; > - for (i=0; i<4; i++) { > - len = dst[index]; > - printf("FPGA: %s\n", &(dst[index+1])); > - index += len+3; > - } > - putc ('\n'); > - /* delayed reboot */ > - for (i=5; i>0; i--) { > - printf("Rebooting in %2d seconds \r",i); > - for (index=0;index<1000;index++) > - udelay(1000); > - } > - putc('\n'); > - do_reset(NULL, 0, 0, NULL); > - } > - > - puts("FPGA: "); > - > - /* display infos on fpgaimage */ > - index = 15; > - for (i=0; i<4; i++) { > - len = dst[index]; > - printf("%s ", &(dst[index+1])); > - index += len+3; > - } > - putc('\n'); > - > - free(dst); > - > - /* > - * Reset FPGA > - */ > - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET); > - udelay(10); > - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET); > - > - return (0); > -} > - > -int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) > -{ > - ulong addr; > - > - if (argc < 2) > - return cmd_usage(cmdtp); > - > - addr = simple_strtoul(argv[1], NULL, 16); > - > - return do_fpga_boot((unsigned char *)addr); > -} > - > -U_BOOT_CMD( > - fpga, 2, 0, do_fpga, > - "boot FPGA", > - "address size\n - boot FPGA with gzipped image at <address>" > -); > - > -#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) > -extern struct pci_controller hose; > -extern void pci_ixp_init(struct pci_controller * hose); > - > -void pci_init_board(void) > -{ > - extern void pci_ixp_init (struct pci_controller *hose); > - > - pci_ixp_init(&hose); > -} > -#endif > diff --git a/boards.cfg b/boards.cfg > index 9fc77fb..cc58de4 100644 > --- a/boards.cfg > +++ b/boards.cfg > @@ -362,8 +362,6 @@ Active arm ixp - - > actux1 > Active arm ixp - - actux1 > actux1_4_32 actux1:FLASH2X2,RAM_32MB > > Michael Schwingen <mich...@schwingen.org> > Active arm ixp - - actux1 > actux1_8_16 actux1:FLASH1X8 > > Michael Schwingen <mich...@schwingen.org> > Active arm ixp - - actux1 > actux1_8_32 actux1:FLASH1X8,RAM_32MB > > Michael Schwingen <mich...@schwingen.org> > -Active arm ixp - prodrive pdnb3 > pdnb3 - > > Stefan Roese <s...@denx.de> > -Active arm ixp - prodrive pdnb3 > scpu pdnb3:SCPU > > Stefan Roese <s...@denx.de> > Active arm pxa - - - > balloon3 - > > Marek Vasut <marek.va...@gmail.com> > Active arm pxa - - - > h2200 - > > Lukasz Dalek <luk0...@gmail.com> > Active arm pxa - - - > palmld - > > Marek Vasut <marek.va...@gmail.com> > diff --git a/doc/README.scrapyard b/doc/README.scrapyard > index 87b1dfe..1f38611 100644 > --- a/doc/README.scrapyard > +++ b/doc/README.scrapyard > @@ -11,6 +11,8 @@ easily if here is something they might want to dig for... > > Board Arch CPU Commit Removed Last > known maintainer/contact > > ================================================================================================= > +pdnb3 arm ixp - 2013-09-24 Stefan > Roese <s...@denx.de> > +scpu arm ixp - 2013-09-24 Stefan > Roese <s...@denx.de> > CANBT powerpc 405CR - - Matthias > Fuchs <matthias.fu...@esd.eu> > Alaska8220 powerpc mpc8220 d6ed322 2013-05-11 > Yukon8220 powerpc mpc8220 d6ed322 2013-05-11 > diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h > deleted file mode 100644 > index c664010..0000000 > --- a/include/configs/pdnb3.h > +++ /dev/null > @@ -1,322 +0,0 @@ > -/* > - * (C) Copyright 2006-2007 > - * Stefan Roese, DENX Software Engineering, s...@denx.de. > - * > - * Configuation settings for the PDNB3 board. > - * > - * SPDX-License-Identifier: GPL-2.0+ > - */ > - > -#ifndef __CONFIG_H > -#define __CONFIG_H > - > -/* > - * High Level Configuration Options > - * (easy to change) > - */ > -#define CONFIG_IXP425 1 /* This is an IXP425 CPU > */ > -#define CONFIG_PDNB3 1 /* on an PDNB3 board */ > - > -#define CONFIG_MACH_TYPE 1002 > - > -#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) > */ > -#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ > - > -/* > - * Ethernet > - */ > -#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */ > -#define CONFIG_PHY_ADDR 16 /* NPE0 PHY address > */ > -#define CONFIG_HAS_ETH1 > -#define CONFIG_PHY1_ADDR 18 /* NPE1 PHY address */ > -#define CONFIG_MII 1 /* MII PHY management */ > -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx > buffers & descriptors */ > - > -/* > - * Misc configuration options > - */ > -#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit > */ > -#define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram > */ > - > -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ > -#define CONFIG_SETUP_MEMORY_TAGS 1 > -#define CONFIG_INITRD_TAG 1 > - > -/* > - * Size of malloc() pool > - */ > -#define CONFIG_SYS_MALLOC_LEN (1 << 20) > - > -/* allow to overwrite serial and ethaddr */ > -#define CONFIG_ENV_OVERWRITE > - > -#define CONFIG_IXP_SERIAL > -#define CONFIG_BAUDRATE 115200 > -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for > console */ > - > - > -/* > - * BOOTP options > - */ > -#define CONFIG_BOOTP_BOOTFILESIZE > -#define CONFIG_BOOTP_BOOTPATH > -#define CONFIG_BOOTP_GATEWAY > -#define CONFIG_BOOTP_HOSTNAME > - > - > -/* > - * Command line configuration. > - */ > -#include <config_cmd_default.h> > - > -#define CONFIG_CMD_DHCP > -#define CONFIG_CMD_DATE > -#define CONFIG_CMD_NET > -#define CONFIG_CMD_MII > -#define CONFIG_CMD_I2C > -#define CONFIG_CMD_ELF > -#define CONFIG_CMD_PING > - > -#if !defined(CONFIG_SCPU) > -#define CONFIG_CMD_NAND > -#endif > - > - > -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ > -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ > - > -/* > - * Miscellaneous configurable options > - */ > -#define CONFIG_SYS_LONGHELP /* undef to save > memory */ > -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt > */ > -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer > Size */ > -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) > /* Print Buffer Size */ > -#define CONFIG_SYS_MAXARGS 16 /* max number of > command args */ > -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot > Argument Buffer Size */ > - > -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on > */ > -#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM > */ > -#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load > address */ > - > -#define CONFIG_IXP425_TIMER_CLK 66666666 > -#define CONFIG_SYS_HZ 1000 /* decrementer > freq: 1 ms ticks */ > - > -/*************************************************************** > - * Platform/Board specific defines start here. > - ***************************************************************/ > - > -/*----------------------------------------------------------------------- > - * Default configuration (environment varibles...) > - *----------------------------------------------------------------------*/ > -#define CONFIG_PREBOOT "echo;" \ > - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ > - "echo" > - > -#undef CONFIG_BOOTARGS > - > -#define CONFIG_EXTRA_ENV_SETTINGS > \ > - "netdev=eth0\0" \ > - "hostname=pdnb3\0" \ > - "nfsargs=setenv bootargs root=/dev/nfs rw " \ > - "nfsroot=${serverip}:${rootpath}\0" \ > - "ramargs=setenv bootargs root=/dev/ram rw\0" \ > - "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \ > - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ > - ":${hostname}:${netdev}:off panic=1\0" \ > - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate} " \ > - "mtdparts=${mtdparts}\0" \ > - "flash_nfs=run nfsargs addip addtty;" \ > - "bootm ${kernel_addr}\0" \ > - "flash_self=run ramargs addip addtty;" \ > - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ > - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ > - "bootm\0" \ > - "rootpath=/opt/buildroot\0" \ > - "bootfile=/tftpboot/netbox/uImage\0" \ > - "kernel_addr=50080000\0" \ > - "ramdisk_addr=50200000\0" \ > - "load=tftp 100000 /tftpboot/netbox/u-boot.bin\0" \ > - "update=protect off 50000000 5007dfff;era 50000000 5007dfff;" \ > - "cp.b 100000 50000000 ${filesize};" \ > - "setenv filesize;saveenv\0" \ > - "upd=run load update\0" \ > - "ipaddr=10.0.0.233\0" \ > - "serverip=10.0.0.152\0" \ > - "netmask=255.255.0.0\0" \ > - "ethaddr=c6:6f:13:36:f3:81\0" \ > - "eth1addr=c6:6f:13:36:f3:82\0" \ > - "mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env)," \ > - "4k@508k(renv)\0" \ > - "" > -#define CONFIG_BOOTCOMMAND "run net_nfs" > - > -/* > - * Physical Memory Map > - */ > -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ > -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ > -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ > - > -#define CONFIG_SYS_TEXT_BASE 0x50000000 > -#define CONFIG_SYS_FLASH_BASE 0x50000000 > -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE > -#if defined(CONFIG_SCPU) > -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 512 > kB for Monitor */ > -#else > -#define CONFIG_SYS_MONITOR_LEN (504 << 10) /* Reserve 512 > kB for Monitor */ > -#endif > - > -/* > - * Expansion bus settings > - */ > -#if defined(CONFIG_SCPU) > -#define CONFIG_SYS_EXP_CS0 0x94d23C42 /* 8bit, max size > */ > -#else > -#define CONFIG_SYS_EXP_CS0 0x94913C43 /* 8bit, max size > */ > -#endif > -#define CONFIG_SYS_EXP_CS1 0x85000043 /* 8bit, 512bytes > */ > - > -/* > - * SDRAM settings > - */ > -#define CONFIG_SYS_SDR_CONFIG 0x18 > -#define CONFIG_SYS_SDR_MODE_CONFIG 0x1 > -#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a > - > -/* > - * FLASH and environment organization > - */ > -#if defined(CONFIG_SCPU) > -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI > compatible */ > -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI > driver */ > -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on > IXP4xx */ > -#endif > - > -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank > #0 */ > - > -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks > */ > -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one > chip */ > - > -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in > ms) */ > -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in > ms) */ > - > -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size > (width) */ > -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for > flash config cycles */ > -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for > flash config cycles */ > -/* > - * The following defines are added for buggy IOP480 byte interface. > - * All other boards should use the standard values (CPCI405 etc.) > - */ > -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard > */ > -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard > */ > -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard > */ > - > -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector > on flinfo */ > - > -#define CONFIG_ENV_IS_IN_FLASH 1 > - > -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + > CONFIG_SYS_MONITOR_LEN) > -#if defined(CONFIG_SCPU) > -/* no redundant environment on SCPU */ > -#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector > */ > -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment > Sector */ > -#else > -#define CONFIG_ENV_SECT_SIZE 0x1000 /* size of one complete sector > */ > -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment > Sector */ > - > -/* Address and size of Redundant Environment Sector */ > -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) > -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) > -#endif > - > -#if !defined(CONFIG_SCPU) > -/* > - * NAND-FLASH stuff > - */ > -#define CONFIG_SYS_MAX_NAND_DEVICE 1 > -#define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base > Address */ > -#endif > - > -/* > - * GPIO settings > - */ > - > -/* FPGA program pin configuration */ > -#define CONFIG_SYS_GPIO_PRG 12 /* FPGA program pin > (cpu output)*/ > -#define CONFIG_SYS_GPIO_CLK 10 /* FPGA clk pin (cpu > output) */ > -#define CONFIG_SYS_GPIO_DATA 14 /* FPGA data pin (cpu > output) */ > -#define CONFIG_SYS_GPIO_INIT 13 /* FPGA init pin (cpu > input) */ > -#define CONFIG_SYS_GPIO_DONE 11 /* FPGA done pin (cpu > input) */ > - > -/* other GPIO's */ > -#define CONFIG_SYS_GPIO_RESTORE_INT 0 > -#define CONFIG_SYS_GPIO_RESTART_INT 1 > -#define CONFIG_SYS_GPIO_SYS_RUNNING 2 > -#define CONFIG_SYS_GPIO_PCI_INTA 3 > -#define CONFIG_SYS_GPIO_PCI_INTB 4 > -#define CONFIG_SYS_GPIO_I2C_SCL 6 > -#define CONFIG_SYS_GPIO_I2C_SDA 7 > -#define CONFIG_SYS_GPIO_FPGA_RESET 9 > -#define CONFIG_SYS_GPIO_CLK_33M 15 > - > -/* > - * I2C stuff > - */ > - > -/* enable I2C and select the hardware/software driver */ > -#define CONFIG_SYS_I2C > -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ > -#define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */ > -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE > -/* > - * Software (bit-bang) I2C driver configuration > - */ > -#define PB_SCL (1 << CONFIG_SYS_GPIO_I2C_SCL) > -#define PB_SDA (1 << CONFIG_SYS_GPIO_I2C_SDA) > - > -#define I2C_INIT GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SCL) > -#define I2C_ACTIVE GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SDA) > -#define I2C_TRISTATE GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_I2C_SDA) > -#define I2C_READ ((*IXP425_GPIO_GPINR & PB_SDA) != 0) > -#define I2C_SDA(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SDA); > \ > - else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SDA) > -#define I2C_SCL(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SCL); > \ > - else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SCL) > -#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */ > - > -/* > - * I2C RTC > - */ > -#if 0 /* test-only */ > -#define CONFIG_RTC_DS1340 1 > -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 > -#else > -/* M41T11 Serial Access Timekeeper(R) SRAM */ > -#define CONFIG_RTC_M41T11 1 > -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 > -#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with the linux > driver */ > -#endif > - > -/* > - * Spartan3 FPGA configuration support > - */ > -#define CONFIG_SYS_FPGA_MAX_SIZE 700*1024 /* 700kByte for > XC3S500E */ > - > -#define CONFIG_SYS_FPGA_PRG (1 << CONFIG_SYS_GPIO_PRG) /* FPGA program > pin (cpu output)*/ > -#define CONFIG_SYS_FPGA_CLK (1 << CONFIG_SYS_GPIO_CLK) /* FPGA clk pin > (cpu output) */ > -#define CONFIG_SYS_FPGA_DATA (1 << CONFIG_SYS_GPIO_DATA) /* FPGA data > pin (cpu output) */ > -#define CONFIG_SYS_FPGA_INIT (1 << CONFIG_SYS_GPIO_INIT) /* FPGA init > pin (cpu input) */ > -#define CONFIG_SYS_FPGA_DONE (1 << CONFIG_SYS_GPIO_DONE) /* FPGA done > pin (cpu input) */ > - > -/* > - * Cache Configuration > - */ > -#define CONFIG_SYS_CACHELINE_SIZE 32 > - > -/* additions for new relocation code, must be added to all boards */ > -#define CONFIG_SYS_SDRAM_BASE 0x00000000 > -#define CONFIG_SYS_INIT_SP_ADDR \ > - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) > - > -#endif /* __CONFIG_H */ Applied to u-boot-arm/master with a trivial am resolution and an on-the-fly update to omap1510inn in doc/README.scrapyard, thanks! Amicalement, -- Albert. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot