Dear Marek,
On 10/13/2013 05:20 PM, Marek Vasut wrote:
Do not reconfigure the FEC clock during board_eth_init(), otherwise
the FEC might have stability issues, refuse to autonegotiate link
entirely or even corrupt packets while indicating correct checksum
on them. Instead, move the FEC clock init to board_early_init_f(),
where all the other upstream clock are initialized and also make
sure there is proper stabilization delay.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Fabio Estevam <fabio.este...@freescale.com>
Cc: Hector Palacios <hector.palac...@digi.com>
Cc: Oliver Metz <oli...@freetz.org>
Cc: Otavio Salvador <ota...@ossystems.com.br>
Cc: Stefano Babic <sba...@denx.de>
Cc: Tom Rini <tr...@ti.com>
---
board/bluegiga/apx4devkit/apx4devkit.c | 10 ++++------
board/denx/m28evk/m28evk.c | 21 +++++++++++----------
board/freescale/mx28evk/mx28evk.c | 9 +++++----
board/schulercontrol/sc_sps_1/sc_sps_1.c | 19 +++++++++++--------
4 files changed, 31 insertions(+), 28 deletions(-)
[...]
diff --git a/board/freescale/mx28evk/mx28evk.c
b/board/freescale/mx28evk/mx28evk.c
index 5005fe2..2c93c44 100644
--- a/board/freescale/mx28evk/mx28evk.c
+++ b/board/freescale/mx28evk/mx28evk.c
@@ -41,6 +41,11 @@ int board_early_init_f(void)
/* SSP2 clock at 160MHz */
mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
+#ifdef CONFIG_CMD_NET
+ cpu_eth_init(NULL);
+ udelay(10000);
+#endif
+
#ifdef CONFIG_CMD_USB
mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 |
@@ -102,10 +107,6 @@ int board_eth_init(bd_t *bis)
struct eth_device *dev;
int ret;
- ret = cpu_eth_init(bis);
- if (ret)
- return ret;
-
/* MX28EVK uses ENET_CLK PAD to drive FEC clock */
writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
&clkctrl_regs->hw_clkctrl_enet);
Why didn't you move the clk enable instruction on mx28evk, as you did with the rest of
platforms?
Best regards,
--
Hector Palacios
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