The value MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET that was used to initialize
the CCGR3 register caused an undefined value for CG0.
Signed-off-by: Pierre Aubert <p.aub...@staubli.com>
CC: Stefano Babic <sba...@denx.de>
---
arch/arm/cpu/armv7/mx6/clock.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 7efb0d2..0f7bcbc 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -457,7 +457,7 @@ void enable_ipu_clock(void)
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
int reg;
reg = readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
+ reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
writel(reg, &mxc_ccm->CCGR3);
}
/***************************************************/
--
1.7.6.5
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