This allows to share some common code for the boards that use a corenet
base SoC.
Two different versions of the function are available in
fsl_corenet_serdes.c and fsl_corenet2_serdes.c files.
Signed-off-by: Valentin Longchamp <valentin.longch...@keymile.com>
---
Changes in v2: None
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 21 +++++++++++++++++++++
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 17 +++++++++++++++++
arch/powerpc/include/asm/fsl_serdes.h | 1 +
board/freescale/b4860qds/b4860qds.c | 16 ----------------
board/freescale/corenet_ds/corenet_ds.c | 14 --------------
board/freescale/p2041rdb/p2041rdb.c | 14 --------------
board/freescale/t4qds/t4qds.c | 16 ----------------
7 files changed, 39 insertions(+), 60 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 93eca76..ff78070 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -201,3 +201,24 @@ void fsl_serdes_init(void)
#endif
}
+
+const char *serdes_clock_to_string(u32 clock)
+{
+ switch (clock) {
+ case SRDS_PLLCR0_RFCK_SEL_100:
+ return "100";
+ case SRDS_PLLCR0_RFCK_SEL_125:
+ return "125";
+ case SRDS_PLLCR0_RFCK_SEL_156_25:
+ return "156.25";
+ case SRDS_PLLCR0_RFCK_SEL_161_13:
+ return "161.1328123";
+ default:
+#if defined(CONFIG_T4240QDS)
+ return "???";
+#else
+ return "122.88";
+#endif
+ }
+}
+
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index b621adf..4bee5bc 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -874,3 +874,20 @@ void fsl_serdes_init(void)
}
#endif
}
+
+const char *serdes_clock_to_string(u32 clock)
+{
+ switch (clock) {
+ case SRDS_PLLCR0_RFCK_SEL_100:
+ return "100";
+ case SRDS_PLLCR0_RFCK_SEL_125:
+ return "125";
+ case SRDS_PLLCR0_RFCK_SEL_156_25:
+ return "156.25";
+ case SRDS_PLLCR0_RFCK_SEL_161_13:
+ return "161.1328123";
+ default:
+ return "150";
+ }
+}
+
diff --git a/arch/powerpc/include/asm/fsl_serdes.h
b/arch/powerpc/include/asm/fsl_serdes.h
index ccb91fb..dfac186 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -99,6 +99,7 @@ enum srds {
int is_serdes_configured(enum srds_prtcl device);
void fsl_serdes_init(void);
+const char *serdes_clock_to_string(u32 clock);
#ifdef CONFIG_FSL_CORENET
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
diff --git a/board/freescale/b4860qds/b4860qds.c
b/board/freescale/b4860qds/b4860qds.c
index e9817c0..b46482a 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -367,22 +367,6 @@ static int serdes_refclock(u8 sw, u8 sdclk)
return ret;
}
-static const char *serdes_clock_to_string(u32 clock)
-{
- switch (clock) {
- case SRDS_PLLCR0_RFCK_SEL_100:
- return "100";
- case SRDS_PLLCR0_RFCK_SEL_125:
- return "125";
- case SRDS_PLLCR0_RFCK_SEL_156_25:
- return "156.25";
- case SRDS_PLLCR0_RFCK_SEL_161_13:
- return "161.13";
- default:
- return "122.88";
- }
-}
-
#define NUM_SRDS_BANKS 2
int misc_init_r(void)
diff --git a/board/freescale/corenet_ds/corenet_ds.c
b/board/freescale/corenet_ds/corenet_ds.c
index 33e2aa5..d6ad3a3 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -148,20 +148,6 @@ int board_early_init_r(void)
return 0;
}
-static const char *serdes_clock_to_string(u32 clock)
-{
- switch(clock) {
- case SRDS_PLLCR0_RFCK_SEL_100:
- return "100";
- case SRDS_PLLCR0_RFCK_SEL_125:
- return "125";
- case SRDS_PLLCR0_RFCK_SEL_156_25:
- return "156.25";
- default:
- return "150";
- }
-}
-
#define NUM_SRDS_BANKS 3
int misc_init_r(void)
diff --git a/board/freescale/p2041rdb/p2041rdb.c
b/board/freescale/p2041rdb/p2041rdb.c
index 44d3e0c..f61dd64 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -186,20 +186,6 @@ unsigned long get_board_sys_clk(unsigned long dummy)
}
}
-static const char *serdes_clock_to_string(u32 clock)
-{
- switch (clock) {
- case SRDS_PLLCR0_RFCK_SEL_100:
- return "100";
- case SRDS_PLLCR0_RFCK_SEL_125:
- return "125";
- case SRDS_PLLCR0_RFCK_SEL_156_25:
- return "156.25";
- default:
- return "150";
- }
-}
-
#define NUM_SRDS_BANKS 2
int misc_init_r(void)
diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
index 3ec1509..44be6b3 100644
--- a/board/freescale/t4qds/t4qds.c
+++ b/board/freescale/t4qds/t4qds.c
@@ -595,22 +595,6 @@ unsigned long get_board_ddr_clk(void)
return 66666666;
}
-static const char *serdes_clock_to_string(u32 clock)
-{
- switch (clock) {
- case SRDS_PLLCR0_RFCK_SEL_100:
- return "100";
- case SRDS_PLLCR0_RFCK_SEL_125:
- return "125";
- case SRDS_PLLCR0_RFCK_SEL_156_25:
- return "156.25";
- case SRDS_PLLCR0_RFCK_SEL_161_13:
- return "161.1328125";
- default:
- return "???";
- }
-}
-
int misc_init_r(void)
{
u8 sw;
--
1.8.0.1
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