Fix problems in chip select selection in imx23,28 spi code
The spi function code for imx23,28 currently does not work for chip select
other than 0.
This is because the register HW_SSP_CTRL0 is first reset and the code does not
load the CS bits
again into HW_SSP_CTRL0 after the reset. The proposed fix reloads the CS bits
after the reset.
Signed-off-by: Asok Subramanian <asok at vyassoft.com>
---
drivers/spi/mxs_spi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 3cf7142..15681dc 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -32,6 +32,7 @@ struct mxs_spi_slave {
uint32_t max_khz;
uint32_t mode;
struct mxs_ssp_regs *regs;
+ unsigned int cs;
};
static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
@@ -74,6 +75,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned
int cs,
mxs_slave->max_khz = max_hz / 1000;
mxs_slave->mode = mode;
mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
+ mxs_slave->cs = cs;
ssp_regs = mxs_slave->regs;
reg = readl(&ssp_regs->hw_ssp_ctrl0);
@@ -102,7 +104,7 @@ int spi_claim_bus(struct spi_slave *slave)
mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
- writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
+ writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT | (mxs_slave->cs) <<
MXS_SSP_CHIPSELECT_SHIFT, &ssp_regs->hw_ssp_ctrl0);
reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
--
1.7.9.5_______________________________________________
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