On Tue, Aug 20, 2013 at 06:47:36PM +0530, Sricharan R wrote: > Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using > software leveling. This was done since hardware leveling was not > working. Now that the right sequence to do hw leveling is identified, > use it. This is required for EMIF clockdomain to idle and come back > during lowpower usecases. [snip] > #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
OK, so this reminds me, should we be printing out something more now then, when we're calculating timings, rather than using precalculated ones? Or is that a different issue I'm thinking of? -- Tom
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