From: Soren Brinkmann <soren.brinkm...@xilinx.com> Some versions of the Zynq first stage boot loader enable PCAP loopback during boot regardless of whether or not the boot image includes PL configuration. This behavior only appears in certain boot modes (notably QSPI boot). Attempting to configure the PL with the loopback bit set will result in timeouts and will prevent successful configuration.
In order to avoid this problem, and to avoid dependency on the version
of the FSBL used to boot the system, ensure that the loopback enable bit
is cleared when loading the driver.
Signed-off-by: Soren Brinkmann <soren.brinkm...@xilinx.com>
Signed-off-by: Michal Simek <michal.si...@xilinx.com>
---
drivers/fpga/zynqpl.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 6a5764f..7f5d90f 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -39,6 +39,7 @@
#define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000
#define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
#define DEVCFG_STATUS_PCFG_INIT 0x00000010
+#define DEVCFG_MCTRL_PCAP_LPBK 0x00000010
#define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002
#define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
@@ -216,6 +217,9 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t
bsize)
swap = SWAP_DONE;
}
+ /* Clear loopback bit */
+ clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
+
if (!partialbit) {
zynq_slcr_devcfg_disable();
--
1.8.2.3
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