From: Matt Porter <matt.por...@linaro.org>
Add QSPI definitions and clock configuration support.
Signed-off-by: Matt Porter <matt.por...@linaro.org>
Signed-off-by: Sourav Poddar <sourav.pod...@ti.com>
---
arch/arm/cpu/armv7/omap5/hw_data.c | 7 +++++++
arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 +
arch/arm/include/asm/arch-omap5/omap.h | 3 +++
arch/arm/include/asm/arch-omap5/spl.h | 1 +
arch/arm/include/asm/omap_common.h | 1 +
5 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 07b1108..4d0eb45 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -425,6 +425,9 @@ void enable_basic_clocks(void)
(*prcm)->cm_wkup_wdtimer2_clkctrl,
(*prcm)->cm_l4per_uart3_clkctrl,
(*prcm)->cm_l4per_i2c1_clkctrl,
+ #ifdef CONFIG_TI_QSPI
+ (*prcm)->cm_l4per_qspi_clkctrl,
+ #endif
0
};
@@ -453,6 +456,10 @@ void enable_basic_clocks(void)
clk_modules_explicit_en_essential,
1);
+#ifdef CONFIG_TI_QSPI
+ setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
+#endif
+
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index e839ff5..7d41744 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -942,6 +942,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_l4per_gpio8_clkctrl = 0x4a009818,
.cm_l4per_mmcsd3_clkctrl = 0x4a009820,
.cm_l4per_mmcsd4_clkctrl = 0x4a009828,
+ .cm_l4per_qspi_clkctrl = 0x4a009838,
.cm_l4per_uart1_clkctrl = 0x4a009840,
.cm_l4per_uart2_clkctrl = 0x4a009848,
.cm_l4per_uart3_clkctrl = 0x4a009850,
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index 5e6d82e..30c913e 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -77,6 +77,9 @@
/* GPMC */
#define OMAP54XX_GPMC_BASE 0x50000000
+/* QSPI */
+#define QSPI_BASE 0x4B300000
+
/*
* Hardware Register Details
*/
diff --git a/arch/arm/include/asm/arch-omap5/spl.h
b/arch/arm/include/asm/arch-omap5/spl.h
index d4d353c..8905cb8 100644
--- a/arch/arm/include/asm/arch-omap5/spl.h
+++ b/arch/arm/include/asm/arch-omap5/spl.h
@@ -31,6 +31,7 @@
#define BOOT_DEVICE_MMC1 5
#define BOOT_DEVICE_MMC2 6
#define BOOT_DEVICE_MMC2_2 7
+#define BOOT_DEVICE_SPI 10
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index 0dbe81b..e37de8c 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -281,6 +281,7 @@ struct prcm_regs {
u32 cm_l4per_mmcsd4_clkctrl;
u32 cm_l4per_msprohg_clkctrl;
u32 cm_l4per_slimbus2_clkctrl;
+ u32 cm_l4per_qspi_clkctrl;
u32 cm_l4per_uart1_clkctrl;
u32 cm_l4per_uart2_clkctrl;
u32 cm_l4per_uart3_clkctrl;
--
1.7.1
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