On Thu, Jul 11, 2013 at 8:03 PM, Marek Vasut <ma...@denx.de> wrote: > The MX28 multi-layer AHB bus can be too slow and trigger the > FEC DMA too early, before all the data hit the DRAM. This patch > ensures the data are written in the RAM before the DMA starts. > Please see the comment in the patch for full details. > > This patch was produced with an amazing help from Albert Aribaud, > who pointed out it can possibly be such a bus synchronisation > issue. > > Signed-off-by: Marek Vasut <ma...@denx.de> > Cc: Albert ARIBAUD <albert.u.b...@aribaud.net> > Cc: Fabio Estevam <fabio.este...@freescale.com> > Cc: Stefano Babic <sba...@denx.de>
Excellent, managed to transfer 90MB via TFTP on mx28evk without a single timeout. Tested-by: Fabio Estevam <fabio.este...@freescale.com> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
