Read the flash bank addr register to get the state of bank in
a perticular flash. and also bank write happens only when there is
a change in bank selection from user.
bank read only valid for flashes which has > 16Mbytes those are
opearted in 3-byte addr mode, each bank occupies 16Mytes.
Suppose if the flash has 64Mbytes size consists of 4 banks like
bank0, bank1, bank2 and bank3.
Signed-off-by: Jagannadha Sutradharudu Teki <jaga...@xilinx.com>
Reviewed-by: Simon Glass <s...@chromium.org>
---
Changes for v5:
- bank_read_cmd <= bank_cmd[0]
- bank_write_cmd <= bank_cmd[1]
Changes for v4:
- Added spi_flash_bank_config
Changes for v3:
- none
Changes for v2:
- none
drivers/mtd/spi/spi_flash.c | 27 +++++++++++++++++++++++++++
drivers/mtd/spi/spi_flash_internal.h | 2 ++
include/spi_flash.h | 2 ++
3 files changed, 31 insertions(+)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 7e19953..64b57ec 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -283,6 +283,12 @@ int spi_flash_cmd_bankaddr_write(struct spi_flash *flash,
u8 bank_sel)
u8 cmd;
int ret;
+ if (flash->bank_curr == bank_sel) {
+ debug("SF: not require to enable bank%d\n", bank_sel);
+ return 0;
+ }
+
+ cmd = flash->bank_write_cmd;
ret = spi_flash_cmd_write_enable(flash);
if (ret < 0) {
debug("SF: enabling write failed\n");
@@ -294,6 +300,7 @@ int spi_flash_cmd_bankaddr_write(struct spi_flash *flash,
u8 bank_sel)
debug("SF: fail to write bank addr register\n");
return ret;
}
+ flash->bank_curr = bank_sel;
ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
if (ret < 0) {
@@ -306,6 +313,9 @@ int spi_flash_cmd_bankaddr_write(struct spi_flash *flash,
u8 bank_sel)
int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0)
{
+ u8 cmd;
+ u8 curr_bank = 0;
+
/* discover bank cmds */
switch (idcode0) {
case SPI_FLASH_SPANSION_IDCODE0:
@@ -322,6 +332,18 @@ int spi_flash_bank_config(struct spi_flash *flash, u8
idcode0)
return -1;
}
+ /* read the bank reg - on which bank the flash is in currently */
+ cmd = flash->bank_read_cmd;
+ if (flash->size > SPI_FLASH_16MB_BOUN) {
+ if (spi_flash_read_common(flash, &cmd, 1, &curr_bank, 1)) {
+ debug("SF: fail to read bank addr register\n");
+ return -1;
+ }
+ flash->bank_curr = curr_bank;
+ } else {
+ flash->bank_curr = curr_bank;
+ }
+
return 0;
}
@@ -469,6 +491,11 @@ struct spi_flash *spi_flash_probe(unsigned int bus,
unsigned int cs,
goto err_manufacturer_probe;
}
+ /* Configure the BAR - disover bank cmds and read current bank */
+ ret = spi_flash_bank_config(flash, *idp);
+ if (ret < 0)
+ goto err_manufacturer_probe;
+
#ifdef CONFIG_OF_CONTROL
if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
debug("SF: FDT decode error\n");
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index db6c444..00ed1ee 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -28,6 +28,8 @@
#define CMD_ERASE_64K 0xd8
#define CMD_ERASE_CHIP 0xc7
+#define SPI_FLASH_16MB_BOUN 0x1000000
+
/* Manufacture ID's */
#define SPI_FLASH_SPANSION_IDCODE0 0x01
#define SPI_FLASH_STMICRO_IDCODE0 0x20
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 38587c2..91b43ee 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -42,6 +42,8 @@ struct spi_flash {
u8 bank_read_cmd;
/* Bank write cmd */
u8 bank_write_cmd;
+ /* Current flash bank */
+ u8 bank_curr;
void *memory_map; /* Address of read-only SPI flash access */
int (*read)(struct spi_flash *flash, u32 offset,
--
1.8.3
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