On 06/13/2013 02:44:17 AM, Chunhe Lan wrote:
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x1fff_ffff DDR 500M
Cacheable
+ * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G
non-cacheable
+ * 0xc000_0000 0xdfff_ffff PCI 512M
non-cacheable
+ * 0xe100_0000 0xe3ff_ffff PCI IO range 4M
non-cacheable
+ * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M
+ *
+ * Localbus non-cacheable
+ *
+ * 0xec00_0000 0xefff_ffff NOR flash 64M NOR
flash
+ * 0xff60_0000 0xff7f_ffff CCSR 2M
non-cacheable
+ * 0xffa0_0000 0xffaf_ffff NAND 1M
non-cacheable
+ * 0xffd0_0000 0xffd0_3fff L1 for stack 16K
Cacheable TLB0
+ */
Same comments as before -- only two of those last four are under the
localbus, and only three are non-cacheable.
Also, DPAA_QBMAN should say "4M cacheable" rather than "4M" for
consistency. Also, please capitalize consistently ("non-cacheable" and
"Cacheable"). :-)
-Scott
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