Commit dc88403 "iomux-v3: Place pad control definitions into common file" broke
mx51_efikamx because it made i.MX6's pad control definitions conflict with
i.MX51's.
i.MX51's pad control definitions are actually common to some other i.MX
(25/35/53), so move them to the common iomux-v3.h (just like what is done in
Linux's), and select the correct definitions depending on whether CONFIG_MX6 is
defined or not.
Signed-off-by: Benoît Thébaudeau <benoit.thebaud...@advansee.com>
---
arch/arm/include/asm/arch-mx5/iomux-mx51.h | 23 -----------------------
arch/arm/include/asm/imx-common/iomux-v3.h | 28 ++++++++++++++++++++++++++++
2 files changed, 28 insertions(+), 23 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx51.h
b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
index 4f37295..5f96dc4 100644
--- a/arch/arm/include/asm/arch-mx5/iomux-mx51.h
+++ b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
@@ -21,27 +21,6 @@
#include <asm/imx-common/iomux-v3.h>
-#define PAD_CTL_DVS (1 << 13)
-#define PAD_CTL_INPUT_DDR (1 << 9)
-#define PAD_CTL_HYS (1 << 8)
-
-#define PAD_CTL_PKE (1 << 7)
-#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
-#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
-
-#define PAD_CTL_ODE (1 << 3)
-
-#define PAD_CTL_DSE_LOW (0 << 1)
-#define PAD_CTL_DSE_MED (1 << 1)
-#define PAD_CTL_DSE_HIGH (2 << 1)
-#define PAD_CTL_DSE_MAX (3 << 1)
-
-#define PAD_CTL_SRE_FAST (1 << 0)
-#define PAD_CTL_SRE_SLOW (0 << 0)
-
/* Pad control groupings */
#define MX51_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH |
\
PAD_CTL_HYS | PAD_CTL_SRE_FAST)
@@ -61,8 +40,6 @@
PAD_CTL_SRE_FAST | PAD_CTL_DVS)
#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE |
PAD_CTL_SRE_FAST)
-#define __NA_ 0x000
-
/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h
b/arch/arm/include/asm/imx-common/iomux-v3.h
index 7b1580d..87d849a 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -23,6 +23,8 @@
#ifndef __MACH_IOMUX_V3_H__
#define __MACH_IOMUX_V3_H__
+#include <common.h>
+
/*
* build IOMUX_PAD structure
*
@@ -95,6 +97,8 @@ typedef u64 iomux_v3_cfg_t;
#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
+#ifdef CONFIG_MX6
+
#define PAD_CTL_HYS (1 << 16)
#define PAD_CTL_PUS_100K_DOWN (0 << 14)
#define PAD_CTL_PUS_47K_UP (1 << 14)
@@ -115,10 +119,34 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_DSE_48ohm (5 << 3)
#define PAD_CTL_DSE_40ohm (6 << 3)
#define PAD_CTL_DSE_34ohm (7 << 3)
+
+#else
+
+#define PAD_CTL_DVS (1 << 13)
+#define PAD_CTL_INPUT_DDR (1 << 9)
+#define PAD_CTL_HYS (1 << 8)
+
+#define PAD_CTL_PKE (1 << 7)
+#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
+#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
+
+#define PAD_CTL_ODE (1 << 3)
+
+#define PAD_CTL_DSE_LOW (0 << 1)
+#define PAD_CTL_DSE_MED (1 << 1)
+#define PAD_CTL_DSE_HIGH (2 << 1)
+#define PAD_CTL_DSE_MAX (3 << 1)
+
+#endif
+
#define PAD_CTL_SRE_FAST (1 << 0)
#define PAD_CTL_SRE_SLOW (0 << 0)
#define IOMUX_CONFIG_SION 0x10
+#define __NA_ 0x000
#define NO_MUX_I 0
#define NO_PAD_I 0
--
1.7.10.4
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