Greg, On 08.04.2013 21:54, txcotrader wrote: > Yes, I am working with a 460SX and a board based off of AMCC Eiger > (unsupported as of 2010).
460SX is quite untested these days I'm afraid. I don't have such a board here as well. > IICx_STS Register settings: > 04 = MDBF Full = Master data buffer contains data > 40 = IRQA Active = An IIC interrrupt has been sent to the UIC > > I'm clearing the IIC register early on in my code: > mtdcr(UIC0SR, 0xffffffff); /* clear all */ > mtdcr(UIC0ER, 0x00000000); /* disable all */ > mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ > mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ > mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ > mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ > mtdcr(UIC0SR, 0xffffffff); /* clear all */ > > mtdcr(UIC1SR, 0xffffffff); /* clear all */ > mtdcr(UIC1ER, 0x00000000); /* disable all */ > mtdcr(UIC1CR, 0x00000000); /* all non-critical */ > mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ > mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ > mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ > mtdcr(UIC1SR, 0xffffffff); /* clear all */ Ughh! This is not IIC (I2C) but UIC released code. So its for the interrupt controller and not I2C controller. But nevertheless this should not matter. > I'm really not sure what to look for at this point, any additional tips you > might have would be extremely helpful. I truly appreciate your help to this > point. As mentioned above I don't have such a board here, so I can't really test anything. Sorry. Best regards, Stefan _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
