On 02/08/2013 09:11:57 AM, Simon Glass wrote:
These are available on other architectures, so add them on ppc.
Signed-off-by: Simon Glass <s...@chromium.org>
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/powerpc/include/asm/io.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/powerpc/include/asm/io.h
b/arch/powerpc/include/asm/io.h
index 1f12c29..1bf12f5 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -317,4 +317,12 @@ static inline phys_addr_t virt_to_phys(void *
vaddr)
#endif
}
+/*
+ * TODO: The kernel offers some more advanced versions of barriers,
it might
+ * have some advantages to use them instead of the simple one here.
+ */
+#define dmb() __asm__ __volatile__ ("" : : : "memory")
+#define __iormb() dmb()
+#define __iowmb() dmb()
What is the definition of these? Given that we already have an
architecture-independent barrier(), I assume this is meant to be an
actual hardware barrier rather than a compiler barrier, so this is not
a correct implementation.
-Scott
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