Laxman, On Fri, Feb 8, 2013 at 2:15 AM, Laxman Dewangan <ldewan...@nvidia.com> wrote: > On Thursday 07 February 2013 04:56 AM, Tom Warren wrote: >> >> T114 has a slightly different I2C clock, with a new divisor for >> standard/fast mode and HS mode. Tested on my Dalmore, and the I2C >> clock is 100KHz +/- 3% on my Saleae Logic analyzer. >> >> Signed-off-by: Tom Warren <twar...@nvidia.com> >> --- >> v2: new > > >> */ >> clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, >> - i2c_bus->speed * 2 * 8); >> + i2c_bus->speed * 2 * 8); > > > I think you do not need to multipled by 2 again here. *2 can be remove. > I2C clock divder is U16 type. > > > >> > >> + >> + clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, >> + CLK_MULT_STD_FAST_MODE * (clk_div_std_fast_mode+1) * >> + i2c_bus->speed * 2); > > > Same as above, *2 is not required. I measured the I2C clock on J51 (GEN1_I2C) on my Dalmore, and the clock is indeed 100KHz (+/- 3 Hz).
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