Fix OMAP3 timer handling to 1ms tick and CONFIG_SYS_HZ to 1000. Clean up macros and comments.
Signed-off-by: Dirk Behme <dirk.be...@googlemail.com> Signed-off-by: Manikandan Pillai <mani.pil...@ti.com> --- Changes from Mani's original patch which is replaced by this [1]: * Don't remove overflow handling in get_timer_masked() * Update omap3_zoom1.h, too. * Clean up timer related comments and macros in config files * Don't touch reset_timer_masked() * Switch divider clock divider from 256 to 8 to be able to get 1000Hz * Remove unused udelay_masked() * Minor clean up of get_tbclk() [1] http://lists.denx.de/pipermail/u-boot/2009-March/049012.html This patch is against U-Boot mainline commit 'b3dd629e78870ba2dc9f8032978721c0fa02a856' 'Prepare 2009.03-rc2' cpu/arm_cortexa8/omap3/interrupts.c | 50 +++++++++++------------------------- include/configs/omap3_beagle.h | 11 +++---- include/configs/omap3_evm.h | 15 +++++----- include/configs/omap3_overo.h | 11 +++---- include/configs/omap3_pandora.h | 11 +++---- include/configs/omap3_zoom1.h | 11 +++---- 6 files changed, 43 insertions(+), 66 deletions(-) Index: u-boot-main/cpu/arm_cortexa8/omap3/interrupts.c =================================================================== --- u-boot-main.orig/cpu/arm_cortexa8/omap3/interrupts.c +++ u-boot-main/cpu/arm_cortexa8/omap3/interrupts.c @@ -169,7 +169,16 @@ static ulong timestamp; static ulong lastinc; static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE; -/* nothing really to do with interrupts, just starts up a counter. */ +/* + * Nothing really to do with interrupts, just starts up a counter. + * We run the counter with 13MHz, divided by 8, resulting in timer + * frequency of 1.625MHz. With 32bit counter register, counter + * overflows in ~44min + */ + +/* 13MHz / 8 = 1.625MHz */ +#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PVT)) + int interrupt_init(void) { /* start the counter ticking up, reload value on overflow */ @@ -232,50 +241,25 @@ void udelay(unsigned long usec) void reset_timer_masked(void) { /* reset time, capture current incrementer value time */ - lastinc = readl(&timer_base->tcrr); + lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); timestamp = 0; /* start "advancing" time stamp from 0 */ } ulong get_timer_masked(void) { - ulong now = readl(&timer_base->tcrr); /* current tick value */ + /* current tick value */ + ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); if (now >= lastinc) /* normal mode (non roll) */ /* move stamp fordward with absoulte diff ticks */ timestamp += (now - lastinc); else /* we have rollover of incrementer */ - timestamp += (0xFFFFFFFF - lastinc) + now; + timestamp += ((0xFFFFFFFF / (TIMER_CLOCK / CONFIG_SYS_HZ)) + - lastinc) + now; lastinc = now; return timestamp; } -/* waits specified delay value and resets timestamp */ -void udelay_masked(unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - /* if "big" number, spread normalization to seconds */ - if (usec >= 1000) { - /* start to normalize for usec to ticks per sec */ - tmo = usec / 1000; - /* find number of "ticks" to wait to achieve target */ - tmo *= CONFIG_SYS_HZ; - tmo /= 1000; /* finish normalize. */ - } else { /* else small number, */ - /* don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000 * 1000); - } - endtime = get_timer_masked() + tmo; - - do { - ulong now = get_timer_masked(); - diff = endtime - now; - } while (diff >= 0); -} - /* * This function is derived from PowerPC code (read timebase as long long). * On ARM it just returns the timer value. @@ -291,7 +275,5 @@ unsigned long long get_ticks(void) */ ulong get_tbclk(void) { - ulong tbclk; - tbclk = CONFIG_SYS_HZ; - return tbclk; + return CONFIG_SYS_HZ; } Index: u-boot-main/include/configs/omap3_beagle.h =================================================================== --- u-boot-main.orig/include/configs/omap3_beagle.h +++ u-boot-main/include/configs/omap3_beagle.h @@ -220,14 +220,13 @@ /* load address */ /* - * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by - * 32KHz clk, or from external sig. This rate is divided by a local divisor. + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. */ -#define V_PVT 7 - #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ -#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_PVT 2 /* Divisor: 2^(PVT+1) => 8 */ +#define CONFIG_SYS_HZ 1000 /*----------------------------------------------------------------------- * Stack sizes Index: u-boot-main/include/configs/omap3_evm.h =================================================================== --- u-boot-main.orig/include/configs/omap3_evm.h +++ u-boot-main/include/configs/omap3_evm.h @@ -216,17 +216,16 @@ /* in Hz */ #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ - /* address */ + /* address */ /* - * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by - * 32KHz clk, or from external sig. This rate is divided by a local divisor. + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. */ -#define V_PVT 7 - -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ -#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PVT 2 /* Divisor: 2^(PVT+1) => 8 */ +#define CONFIG_SYS_HZ 1000 /*----------------------------------------------------------------------- * Stack sizes Index: u-boot-main/include/configs/omap3_overo.h =================================================================== --- u-boot-main.orig/include/configs/omap3_overo.h +++ u-boot-main/include/configs/omap3_overo.h @@ -213,14 +213,13 @@ /* address */ /* - * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by - * 32KHz clk, or from external sig. This rate is divided by a local divisor. + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. */ -#define V_PVT 7 - #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ -#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_PVT 2 /* Divisor: 2^(PVT+1) => 8 */ +#define CONFIG_SYS_HZ 1000 /*----------------------------------------------------------------------- * Stack sizes Index: u-boot-main/include/configs/omap3_pandora.h =================================================================== --- u-boot-main.orig/include/configs/omap3_pandora.h +++ u-boot-main/include/configs/omap3_pandora.h @@ -215,14 +215,13 @@ /* address */ /* - * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by - * 32KHz clk, or from external sig. This rate is divided by a local divisor. + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. */ -#define V_PVT 7 - #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ -#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_PVT 2 /* Divisor: 2^(PVT+1) => 8 */ +#define CONFIG_SYS_HZ 1000 /*----------------------------------------------------------------------- * Stack sizes Index: u-boot-main/include/configs/omap3_zoom1.h =================================================================== --- u-boot-main.orig/include/configs/omap3_zoom1.h +++ u-boot-main/include/configs/omap3_zoom1.h @@ -222,14 +222,13 @@ /* load address */ /* - * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by - * 32KHz clk, or from external sig. This rate is divided by a local divisor. + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. */ -#define V_PVT 7 - #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ -#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_PVT 2 /* Divisor: 2^(PVT+1) => 8 */ +#define CONFIG_SYS_HZ 1000 /*----------------------------------------------------------------------- * Stack sizes _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
