On Monday, January 14, 2013, Prabhakar Kushwaha wrote:
> The BSC9132 is a highly integrated device that targets the evolving
> Microcell, Picocell, and Enterprise-Femto base station market subsegments.
>
> The BSC9132 device combines Power Architecture e500 and DSP StarCore
> SC3850
> core technologies with MAPLE-B2P baseband acceleration processing elements
> to address the need for a high performance, low cost, integrated solution
> that handles all required processing layers without the need for an
> external device except for an RF transceiver or, in a Micro base station
> configuration, a host device that handles the L3/L4 and handover between
> sectors.
>
> The BSC9132 SoC includes the following function and features:
> - Power Architecture subsystem including two e500 processors with
> 512-Kbyte shared L2 cache
> - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
> cache
> - 32 Kbyte of shared M3 memory
> - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
> Processing (MAPLE-B2P)
> - Two DDR3/3L memory interfaces with 32-bit data width (40 bits
> including
> ECC), up to 1333 MHz data rate
> - Dedicated security engine featuring trusted boot
> - Two DMA controllers
> - OCNDMA with four bidirectional channels
> - SysDMA with sixteen bidirectional channels
> - Interfaces
> - Four-lane SerDes PHY
> - PCI Express controller complies with the PEX
> Specification-Rev 2.0
> - Two Common Public Radio Interface (CPRI) controller lanes
> - High-speed USB 2.0 host and device controller with ULPI
> interface
> - Enhanced secure digital (SD/MMC) host controller (eSDHC)
> - Antenna interface controller (AIC), supporting four industry
> standard JESD207/four custom ADI RF interfaces
> - ADI lanes support both full duplex FDD support & half duplex TDD
> - Universal Subscriber Identity Module (USIM) interface that
> facilitates communication to SIM cards or Eurochip pre-paid
> phone
> cards
> - Two DUART, two eSPI, and two I2C controllers
> - Integrated Flash memory controller (IFC)
> - GPIO
> - Sixteen 32-bit timers
>
> Signed-off-by: Naveen Burmi <naveenbu...@freescale.com <javascript:;>>
> Signed-off-by: Poonam Aggrwal <poonam.aggr...@freescale.com <javascript:;>
> >
> Signed-off-by: Prabhakar Kushwaha <prabha...@freescale.com <javascript:;>>
> ---
> Changes for v2: Incorporated Timur's review comments
> - Removed SVR_9132_E as it is not required as part of
> following commit
> 48f6a5c348453fc3ab33aaa91e5e4198a28678ff
You didn't test after you did this, did you? This breaks the build.
>
> diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c
> b/arch/powerpc/cpu/mpc8xxx/cpu.c
> index e8613be..03fd2fb 100644
> --- a/arch/powerpc/cpu/mpc8xxx/cpu.c
> +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
> @@ -86,6 +86,9 @@ static struct cpu_type cpu_type_list[] = {
> CPU_TYPE_ENTRY(B4220, B4220, 0),
> CPU_TYPE_ENTRY(BSC9130, 9130, 1),
> CPU_TYPE_ENTRY(BSC9131, 9131, 1),
> + CPU_TYPE_ENTRY(BSC9132, 9132, 2),
> + CPU_TYPE_ENTRY(BSC9132, 9132_E, 2),
You removed the declaration, but not the consumer. Please build-test before
you submit.
Andy
> <http://lists.denx.de/mailman/listinfo/u-boot>
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