Hello Stefan, On Mon, Dec 1, 2008 at 8:46 PM, Stefan Roese <s...@denx.de> wrote: > On Monday 01 December 2008, Leon Woestenberg wrote: >> >> Now, if I re-program the end-point FPGA during the u-boot boot >> >> time-out, Linux will recognize the end-point. >> > >> > It's possible that either the reset in between goes bonkers or something >> > else causes your FPGA to stop responding. It looks like a programming >> > problem with the FPGA to me. >> >> I have verified that the end point does not receive any kind of reset. >> >> Also, this problem only happens on the Canyonlands board; on x86 and >> powerpc MPC8315E it remains properly working after soft/hard resets, >> u-boot init etc. > > This could be because only the 4xx Linux PCI(e) driver really resets the > endpoint (PHY reset). But you seem to have analyzed this already. >
Some progress: Using au-boot GIT checkout of 9-2-2009 (one month old) I now have different behaviour: u-boot does report a link, but no longer the PCIe vendor id: CPU: AMCC PowerPC 460EX Rev. A at 800 MHz (PLB=200, OPB=100, EBC=100 MHz) Security/Kasumi support Bootstrap Option H - Boot ROM Location I2C (Addr 0x52) Internal PCI arbiter disabled 32 kB I-Cache 32 kB D-Cache Board: Canyonlands - AMCC PPC460EX Evaluation Board, 2*PCIe, Rev. 16 I2C: ready DTT: 1 is 44 C DRAM: 512 MB (ECC not enabled, 400 MHz, CL3) FLASH: 64 MB NAND: 128 MiB PCI: Bus Dev VenId DevId Class Int PCIE0: link is not up. PCIE0: initialization as root-complex failed PCIE1: successfully set as root-complex Linux now correctly recognizes the device. The FPGA with PCIe end point now also survives both a hard reset (reset button) and soft reset (shutdown -r now in Linux). Regards, -- Leon _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot