[U-Boot] [PATCH 5/9] EXYNOS5: DWMMC: API to set mmc clock divisor

[Amar]

This API computes the divisor value based on MPLL clock and
writes it into the FSYS1 register.

Signed-off-by: Amar <amarendra...@samsung.com>
---
 arch/arm/cpu/armv7/exynos/clock.c      |   39 ++++++++++++++++++++++++++++++-
 arch/arm/include/asm/arch-exynos/clk.h |    1 +
 2 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c 
b/arch/arm/cpu/armv7/exynos/clock.c
index 731bbff..6517296 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -379,7 +379,7 @@ static unsigned long exynos4_get_mmc_clk(int dev_index)
                (struct exynos4_clock *)samsung_get_base_clock();
        unsigned long uclk, sclk;
        unsigned int sel, ratio, pre_ratio;
-       int shift;
+       int shift = 0;
 
        sel = readl(&clk->src_fsys);
        sel = (sel >> (dev_index << 2)) & 0xf;
@@ -428,7 +428,7 @@ static unsigned long exynos5_get_mmc_clk(int dev_index)
                (struct exynos5_clock *)samsung_get_base_clock();
        unsigned long uclk, sclk;
        unsigned int sel, ratio, pre_ratio;
-       int shift;
+       int shift = 0;
 
        sel = readl(&clk->src_fsys);
        sel = (sel >> (dev_index << 2)) & 0xf;
@@ -526,6 +526,41 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned 
int div)
        writel(val, addr);
 }
 
+/* exynos5: set the mmc clock div ratio in fsys1 */
+int exynos5_mmc_set_clk_div(int dev_index)
+{
+       struct exynos5_clock *clk =
+               (struct exynos5_clock *)samsung_get_base_clock();
+       unsigned int addr;
+       unsigned int clock;
+       unsigned int tmp;
+       unsigned int i;
+
+       /* get mpll clock */
+       clock = get_pll_clk(MPLL) / 1000000;
+
+       /*
+        * CLK_DIV_FSYS1
+        * MMC0_PRE_RATIO [15:8], MMC0_RATIO [3:0]
+        * CLK_DIV_FSYS2
+        * MMC2_PRE_RATIO [15:8], MMC2_RATIO [3:0]
+        */
+       if (dev_index < 2) {
+               addr = (unsigned int)&clk->div_fsys1;
+       } else {
+               addr = (unsigned int)&clk->div_fsys2;
+       }
+
+       tmp = readl(addr) & ~FSYS1_MMC0_DIV_MASK;
+       for (i = 0; i <= 0xf; i++) {
+               if ((clock / (i + 1)) <= 400) {
+                       writel(tmp | i << 0, addr);
+                       break;
+               }
+       }
+       return 0;
+}
+
 /* get_lcd_clk: return lcd clock frequency */
 static unsigned long exynos4_get_lcd_clk(void)
 {
diff --git a/arch/arm/include/asm/arch-exynos/clk.h 
b/arch/arm/include/asm/arch-exynos/clk.h
index ff155d8..b0ecdd4 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -36,6 +36,7 @@ unsigned long get_pwm_clk(void);
 unsigned long get_uart_clk(int dev_index);
 unsigned long get_mmc_clk(int deV_index);
 void set_mmc_clk(int dev_index, unsigned int div);
+int exynos5_mmc_set_clk_div(int dev_index);
 unsigned long get_lcd_clk(void);
 void set_lcd_clk(void);
 void set_mipi_clk(void);
-- 
1.7.0.4

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