On 13 December 2012 11:49, Chander Kashyap <chander.kash...@linaro.org> wrote: > Dear Kim, > > On 12 December 2012 13:24, Jeong Hyeon Kim <snow.jh...@gmail.com> wrote: >> From: Jeong-Hyeon Kim <jh...@insignal.co.kr> >> >> This patch adds the support for Exynos4212/4412. >> >> Samsung's ARM Cortex-A9 based Exynos4x12 SoCs and Exynos4210 are similar. >> Address of a few registers are different in CMU part like MPLL. >> >> Signed-off-by: Jeong-Hyeon Kim <jh...@insignal.co.kr> >> --- >> arch/arm/cpu/armv7/exynos/clock.c | 7 +- >> arch/arm/include/asm/arch-exynos/clock.h | 240 >> ++++++++++++++++++++++++++++++ >> arch/arm/include/asm/arch-exynos/cpu.h | 1 + >> 3 files changed, 247 insertions(+), 1 deletion(-) >> > As i discussed with you these changes has been already posted. > http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/148856 > Kindly use them and resend yours patches. >> diff --git a/arch/arm/cpu/armv7/exynos/clock.c >> b/arch/arm/cpu/armv7/exynos/clock.c >> index fe61f88..47e2e6c 100644 >> --- a/arch/arm/cpu/armv7/exynos/clock.c >> +++ b/arch/arm/cpu/armv7/exynos/clock.c > Please have a look patch at the link. > [PATCH] EXYNOS: EXYNOS4X12: extract Exynos4x12 IPs clock frequency
http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/143640 >> @@ -94,7 +94,12 @@ static unsigned long exynos4_get_pll_clk(int pllreg) >> r = readl(&clk->apll_con0); >> break; >> case MPLL: >> - r = readl(&clk->mpll_con0); >> + if (proid_is_exynos4412()) { >> + struct exynos4412_clock *clk4412 = >> + (struct exynos4412_clock >> *)samsung_get_base_clock(); >> + r = readl(&clk4412->mpll_con0); >> + } else >> + r = readl(&clk->mpll_con0); >> break; >> case EPLL: >> r = readl(&clk->epll_con0); >> diff --git a/arch/arm/include/asm/arch-exynos/clock.h >> b/arch/arm/include/asm/arch-exynos/clock.h >> index ff6781a..5d4ed5c 100644 >> --- a/arch/arm/include/asm/arch-exynos/clock.h >> +++ b/arch/arm/include/asm/arch-exynos/clock.h >> @@ -251,6 +251,246 @@ struct exynos4_clock { >> unsigned int div_iem_l1; >> }; >> >> +struct exynos4412_clock { >> + unsigned char res1[0x4200]; >> + unsigned int src_leftbus; >> + unsigned char res2[0x1fc]; >> + unsigned int mux_stat_leftbus; >> + unsigned char res3[0xfc]; >> + unsigned int div_leftbus; >> + unsigned char res4[0xfc]; >> + unsigned int div_stat_leftbus; >> + unsigned char res5[0x1fc]; >> + unsigned int gate_ip_leftbus; >> + unsigned char res6[0x12c]; >> + unsigned int gate_ip_image; >> + unsigned char res7[0xcc]; >> + unsigned int clkout_cmu_leftbus; >> + unsigned int clkout_cmu_leftbus_div_stat; >> + unsigned char res8[0x37f8]; >> + unsigned int src_rightbus; >> + unsigned char res9[0x1fc]; >> + unsigned int mux_stat_rightbus; >> + unsigned char res10[0xfc]; >> + unsigned int div_rightbus; >> + unsigned char res11[0xfc]; >> + unsigned int div_stat_rightbus; >> + unsigned char res12[0x1fc]; >> + unsigned int gate_ip_rightbus; >> + unsigned char res13[0x15c]; >> + unsigned int gate_ip_perir; >> + unsigned char res14[0x9c]; >> + unsigned int clkout_cmu_rightbus; >> + unsigned int clkout_cmu_rightbus_div_stat; >> + unsigned char res15[0x3608]; >> + unsigned int epll_lock; >> + unsigned char res16[0xc]; >> + unsigned int vpll_lock; >> + unsigned char res17[0xec]; >> + unsigned int epll_con0; >> + unsigned int epll_con1; >> + unsigned int epll_con2; >> + unsigned char res18[0x4]; >> + unsigned int vpll_con0; >> + unsigned int vpll_con1; >> + unsigned int vpll_con2; >> + unsigned char res19[0xe4]; >> + unsigned int src_top0; >> + unsigned int src_top1; >> + unsigned char res20[0x8]; >> + unsigned int src_cam0; >> + unsigned int src_tv; >> + unsigned int src_mfc; >> + unsigned int src_g3d; >> + unsigned char res21[0x4]; >> + unsigned int src_lcd0; >> + unsigned int src_isp; >> + unsigned int src_maudio; >> + unsigned int src_fsys; >> + unsigned char res22[0xc]; >> + unsigned int src_peril0; >> + unsigned int src_peril1; >> + unsigned int src_cam1; >> + unsigned char res23[0xc4]; >> + unsigned int src_mask_cam0; >> + unsigned int src_mask_tv; >> + unsigned char res24[0xc]; >> + unsigned int src_mask_lcd; >> + unsigned int src_mask_isp; >> + unsigned int src_mask_maudio; >> + unsigned int src_mask_fsys; >> + unsigned char res25[0xc]; >> + unsigned int src_mask_peril0; >> + unsigned int src_mask_peril1; >> + unsigned char res26[0xb8]; >> + unsigned int mux_stat_top; >> + unsigned int mux_stat_top1; >> + unsigned char res27[0x10]; >> + unsigned int mux_stat_mfc; >> + unsigned int mux_stat_g3d; >> + unsigned char res28[0x28]; >> + unsigned int mux_stat_cam1; >> + unsigned char res29[0xb4]; >> + unsigned int div_top; >> + unsigned char res30[0xc]; >> + unsigned int div_cam0; >> + unsigned int div_tv; >> + unsigned int div_mfc; >> + unsigned int div_g3d; >> + unsigned char res31[0x4]; >> + unsigned int div_lcd; >> + unsigned int div_isp; >> + unsigned int div_maudio; >> + unsigned int div_fsys0; >> + unsigned int div_fsys1; >> + unsigned int div_fsys2; >> + unsigned int div_fsys3; >> + unsigned int div_peril0; >> + unsigned int div_peril1; >> + unsigned int div_peril2; >> + unsigned int div_peril3; >> + unsigned int div_peril4; >> + unsigned int div_peril5; >> + unsigned int div_cam1; >> + unsigned char res32[0x14]; >> + unsigned int div2_ratio; >> + unsigned char res33[0x8c]; >> + unsigned int div_stat_top; >> + unsigned char res34[0xc]; >> + unsigned int div_stat_cam0; >> + unsigned int div_stat_tv; >> + unsigned int div_stat_mfc; >> + unsigned int div_stat_g3d; >> + unsigned char res35[0x4]; >> + unsigned int div_stat_lcd; >> + unsigned int div_stat_isp; >> + unsigned int div_stat_maudio; >> + unsigned int div_stat_fsys0; >> + unsigned int div_stat_fsys1; >> + unsigned int div_stat_fsys2; >> + unsigned int div_stat_fsys3; >> + unsigned int div_stat_peril0; >> + unsigned int div_stat_peril1; >> + unsigned int div_stat_peril2; >> + unsigned int div_stat_peril3; >> + unsigned int div_stat_peril4; >> + unsigned int div_stat_peril5; >> + unsigned int div_stat_cam1; >> + unsigned char res36[0x14]; >> + unsigned int div2_stat; >> + unsigned char res37[0xc0]; >> + unsigned int gate_bus_fsys1; >> + unsigned char res38[0x1d8]; >> + unsigned int gate_ip_cam; >> + unsigned int gate_ip_tv; >> + unsigned int gate_ip_mfc; >> + unsigned int gate_ip_g3d; >> + unsigned char res39[0x4]; >> + unsigned int gate_ip_lcd; >> + unsigned int gate_ip_isp; >> + unsigned char res40[0x4]; >> + unsigned int gate_ip_fsys; >> + unsigned char res41[0x8]; >> + unsigned int gate_ip_gps; >> + unsigned int gate_ip_peril; >> + unsigned char res42[0x1c]; >> + unsigned int gate_block; >> + unsigned char res43[0x8c]; >> + unsigned int clkout_cmu_top; >> + unsigned int clkout_cmu_top_div_stat; >> + unsigned char res44[0x3600]; >> + unsigned int mpll_lock; >> + unsigned char res45[0xfc]; >> + unsigned int mpll_con0; >> + unsigned int mpll_con1; >> + unsigned char res46[0xf0]; >> + unsigned int src_dmc; >> + unsigned char res47[0xfc]; >> + unsigned int src_mask_dmc; >> + unsigned char res48[0xfc]; >> + unsigned int mux_stat_dmc; >> + unsigned char res49[0xfc]; >> + unsigned int div_dmc0; >> + unsigned int div_dmc1; >> + unsigned char res50[0xf8]; >> + unsigned int div_stat_dmc0; >> + unsigned int div_stat_dmc1; >> + unsigned char res51[0x2f8]; >> + unsigned int gate_ip_dmc; >> + unsigned int gate_ip_dmc1; >> + unsigned char res52[0xf8]; >> + unsigned int clkout_cmu_dmc; >> + unsigned int clkout_cmu_dmc_div_stat; >> + unsigned char res53[0x5f8]; >> + unsigned int dcgidx_map0; >> + unsigned int dcgidx_map1; >> + unsigned int dcgidx_map2; >> + unsigned char res54[0x14]; >> + unsigned int dcgperf_map0; >> + unsigned int dcgperf_map1; >> + unsigned char res55[0x18]; >> + unsigned int dvcidx_map; >> + unsigned char res56[0x1c]; >> + unsigned int freq_cpu; >> + unsigned int freq_dpm; >> + unsigned char res57[0x18]; >> + unsigned int dvsemclk_en; >> + unsigned int maxperf; >> + unsigned char res58[0xc]; >> + unsigned int dmc_puause_ctrl; >> + unsigned int ddrphy_lock_ctrl; >> + unsigned int c2c_state; >> + unsigned char res59[0x2f60]; >> + unsigned int apll_lock; >> + unsigned char res60[0xfc]; >> + unsigned int apll_con0; >> + unsigned int apll_con1; >> + unsigned char res61[0xf8]; >> + unsigned int src_cpu; >> + unsigned char res62[0x1fc]; >> + unsigned int mux_stat_cpu; >> + unsigned char res63[0xfc]; >> + unsigned int div_cpu0; >> + unsigned int div_cpu1; >> + unsigned char res64[0xf8]; >> + unsigned int div_stat_cpu0; >> + unsigned int div_stat_cpu1; >> + unsigned char res65[0x2f8]; >> + unsigned int gate_ip_cpu; >> + unsigned char res66[0xfc]; >> + unsigned int clkout_cmu_cpu; >> + unsigned int clkout_cmu_cpu_div_stat; >> + unsigned char res67[0x5f8]; >> + unsigned int armclk_stopctrl; >> + unsigned int atclk_stopctrl; >> + unsigned char res68[0x18]; >> + unsigned int pwr_ctrl; >> + unsigned int pwr_ctrl2; >> + unsigned char res69[0x3d8]; >> + unsigned int l2_status; >> + unsigned char res70[0xc]; >> + unsigned int cpu_status; >> + unsigned char res71[0xc]; >> + unsigned int ptm_status; >> + unsigned char res72[0x2edc]; >> + unsigned int clk_div_isp0; >> + unsigned int clk_div_isp1; >> + unsigned char res73[0xf8]; >> + unsigned int clk_div_stat_isp0; >> + unsigned int clk_div_stat_isp1; >> + unsigned char res74[0x3f8]; >> + unsigned int gate_ip_isp0; >> + unsigned int gate_ip_isp1; >> + unsigned char res75[0x1f8]; >> + unsigned int clkout_cmu_isp; >> + unsigned int clkout_cmu_isp_stat; >> + unsigned char res76[0xf8]; >> + unsigned int clkout_cmu_spare0; >> + unsigned int clkout_cmu_spare1; >> + unsigned int clkout_cmu_spare2; >> + unsigned int clkout_cmu_spare3; >> +}; >> + >> struct exynos5_clock { >> unsigned int apll_lock; >> unsigned char res1[0xfc]; >> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h >> b/arch/arm/include/asm/arch-exynos/cpu.h >> index d1b2ea8..7ee5366 100644 >> --- a/arch/arm/include/asm/arch-exynos/cpu.h >> +++ b/arch/arm/include/asm/arch-exynos/cpu.h >> @@ -152,6 +152,7 @@ static inline int proid_is_##type(void) >> \ >> } >> >> IS_EXYNOS_TYPE(exynos4210, 0x4210) >> +IS_EXYNOS_TYPE(exynos4412, 0x4412) >> IS_EXYNOS_TYPE(exynos5250, 0x5250) >> >> #define SAMSUNG_BASE(device, base) \ >> -- >> 1.7.9.5 >> > > > > -- > with warm regards, > Chander Kashyap -- with warm regards, Chander Kashyap _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
