+               ulong start = get_timer(0);
+
+               do {
+                       ret = usb_get_port_status(dev, i + 1, portsts);
+                       if (ret<  0) {
+                               USB_HUB_PRINTF("get_port_status failed\n");
+                               break;
+                       }
+
+                       portstatus = le16_to_cpu(portsts->wPortStatus);
+                       portchange = le16_to_cpu(portsts->wPortChange);
+
+                       if ((portchange&  USB_PORT_STAT_C_CONNECTION) ==
+                               (portstatus&  USB_PORT_STAT_CONNECTION))

I don't know if there is any corner case when the above check
will always fail and so it will always wait a maximal delay time.
Are those registers that identical, or can there be differences?

+                               break;
+
+                       mdelay(100);
+               } while (get_timer(start)<  CONFIG_SYS_HZ * 10);

Is there any justification for the CONFIG_SYS_HZ * 10?
I would be much more fine with this patch if there were any
(even just test based * 2) reason for that number.


Not really. Just a practical test.
Marek, can I have comments from you as well

Thanks
Vipin

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