This patch adds clock support for SATA
Signed-off-by: Vasanth Ananthan <vasant...@samsung.com>
---
arch/arm/cpu/armv7/exynos/clock.c | 64 ++++++++++++++++++++++++++++++++
arch/arm/include/asm/arch-exynos/clk.h | 3 +-
2 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index fe61f88..db68ef0 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -26,6 +26,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/clk.h>
#include <asm/arch/periph.h>
+#include <asm/errno.h>
/* Epll Clock division values to achive different frequency output */
static struct set_epll_con_val exynos5_epll_div[] = {
@@ -326,6 +327,53 @@ static unsigned long exynos4_get_uart_clk(int dev_index)
return uclk;
}
+/* Sets clocks related to SATA */
+static int exynos5_set_sata_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ u32 tmp;
+
+ /* Setting src as MPLL_USER */
+ tmp = readl(&clk->src_fsys);
+ tmp &= ~(1 << 24);
+ writel(tmp, &clk->src_fsys);
+
+ /* Unmasking SATA clk */
+ tmp = readl(&clk->src_mask_fsys);
+ tmp |= (1 << 24);
+ writel(tmp, &clk->src_mask_fsys);
+
+ /* Set divider value for getting sclk as 66 MHz */
+ tmp = readl(&clk->div_fsys0);
+ tmp |= (0xB << 20);
+
+ return 0;
+}
+
+/* Returns the clock frequency in Hz */
+static unsigned long exynos5_get_sata_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long uclk, sclk;
+ u32 ratio, tmp;
+
+ tmp = readl(&clk->src_fsys);
+
+ if ((tmp & (1 << 24)) == 0)
+ sclk = get_pll_clk(MPLL);
+ else
+ sclk = get_pll_clk(BPLL);
+
+ ratio = readl(&clk->div_fsys0);
+ ratio = (ratio >> 20) & 0xf;
+
+ uclk = sclk / (ratio + 1);
+
+ return uclk;
+}
+
/* exynos5: return uart clock frequency */
static unsigned long exynos5_get_uart_clk(int dev_index)
{
@@ -963,6 +1011,22 @@ unsigned long get_uart_clk(int dev_index)
return exynos4_get_uart_clk(dev_index);
}
+unsigned long get_sata_clk(void)
+{
+ if (cpu_is_exynos5())
+ return exynos5_get_sata_clk();
+
+ return -ENOSYS;
+}
+
+void set_sata_clk(void)
+{
+ if (cpu_is_exynos5())
+ return exynos5_set_sata_clk();
+
+ return -ENOSYS;
+}
+
void set_mmc_clk(int dev_index, unsigned int div)
{
if (cpu_is_exynos5())
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index cd12323..10f28cc 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -42,5 +42,6 @@ void set_i2s_clk_source(void);
int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq);
int set_epll_clk(unsigned long rate);
int set_spi_clk(int periph_id, unsigned int rate);
-
+unsigned long get_sata_clk(void);
+void set_sata_clk(void);
#endif
--
1.7.9.5
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