> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).a
> +
> +COBJS-y += firetux.o boardrevision.o led.o gpio.o
please split it
> +COBJS-$(CONFIG_CMD_NAND) += nand.o
> +SOBJS-y += lowlevel_init.o memsetup.o relocate.o
please split it
> +
> +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS-y))
> +SOBJS := $(addprefix $(obj),$(SOBJS-y))
> +
> +all: $(LIB)
> +
> +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
> + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
> +
> +clean:
> + rm -f $(SOBJS) $(OBJS)
> +
> +distclean: clean
> + rm -f $(LIB) core *.bak .depend
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/dspg/firetux/boardrevision.c
> b/board/dspg/firetux/boardrevision.c
> new file mode 100644
> index 0000000..3119090
> --- /dev/null
> +++ b/board/dspg/firetux/boardrevision.c
> @@ -0,0 +1,299 @@
> +/*
> + * firetux board detection
> + *
> + * (C) Copyright 2007-2009, emlix GmbH, Germany
> + * Juergen Schoew <j...@emlix.com>
> + * (C) Copyright 2008, Sebastian Hess, emlix GmbH <s...@emlix.com>
> + *
> + * (C) Copyright 2008, DSPG Technologies GmbH, Germany
> + * (C) Copyright 2007, NXP Semiconductors Germany GmbH
> + * Matthias Wenzel, <n...@mazzoo.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/*
> + * These VEGA boards are very similair to each other. The main difference
> + * is the phy address of the network, CPU revision, number of leds and keys.
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include "firetux.h"
> +
> +#ifndef CONFIG_IP3912_ETN1_BASE
> +#define CONFIG_IP3912_ETN1_BASE 0xC1600000
> +#endif
> +#ifndef CONFIG_IP3912_ETN2_BASE
> +#define CONFIG_IP3912_ETN2_BASE 0xC1700000
> +#endif
> +
> +/* ip3912 / pnx8181 ETN registers */
> +#define ETN1_BASE CONFIG_IP3912_ETN1_BASE
> +#define ETN2_BASE CONFIG_IP3912_ETN2_BASE
> +
> +#define ETN_MAC1 0x0000
> +#define ETN_SUPP 0x0018
> +#define ETN_MCFG 0x0020
> +#define ETN_MADR 0x0028
> +#define ETN_MCMD 0x0024
> +#define ETN_MWTD 0x002c
> +#define ETN_MRDD 0x0030
> +#define ETN_MIND 0x0034
> +#define ETN_COMMAND 0x0100
please move to a heaser
> +
> +static char firetux_boardrevision = UNKNOWN_PNX8181;
> +
> +char get_boardrevision(void)
> +{
> + return firetux_boardrevision;
> +}
> +
> +static void detect_etn_start(void)
> +{
> + debug("board detect: initialize ETN\n");
> + /* reset MII mgmt, set MII clock */
> + writel(0x0000801c, (void *)(ETN1_BASE + ETN_MCFG));
> + writel(0x0000001c, (void *)(ETN1_BASE + ETN_MCFG));
> +
> + /* enable RMMI */
> + writel(0x00000600, (void *)(ETN1_BASE + ETN_COMMAND));
> +
> + /* reset MAC layer */
> + writel(0x0000cf00, (void *)(ETN1_BASE + ETN_MAC1));
> + /* release MAC soft reset */
> + writel(0x00000000, (void *)(ETN1_BASE + ETN_MAC1));
> + /* reset rx-path, tx-path, host registers */
> + writel(0x00000638, (void *)(ETN1_BASE + ETN_COMMAND));
> + /* reset RMII, 100Mbps MAC, 10Mbps MAC */
> + writel(0x1888, (void *)(ETN1_BASE + ETN_SUPP));
> + writel(0x1000, (void *)(ETN1_BASE + ETN_SUPP));
> +}
> +
maybe you can add an ifdef arround to not compile it when the network is
desable?
and is these phy functions are board or soc specific?
> +/* Wait for the ETN engine to be ready */
> +static void detect_phy_wait(void)
> +{
> + int i, status;
please an empty line
> + for (i = 0; i < 1000; i++) {
> + status = readl((void *)(ETN1_BASE + ETN_MIND)) & 0x7;
> + if (!status)
> + return;
> + udelay(1);
> + }
> + debug("board detect: wait PHY timed out!\n");
> +}
> +
> +/* write to phy */
> +static void detect_phy_write(u8 address, u8 reg, u16 data)
> +{
> + writel((address << 8) | reg, (void *)(ETN1_BASE + ETN_MADR));
> + writel(data, (ETN1_BASE + ETN_MWTD));
> + detect_phy_wait();
> +}
> +
> +/* read from phy */
> +static u16 detect_phy_read(u8 address, u8 reg)
> +{
> + u16 value;
please an empty line
> + writel((address << 8) | reg, (void *)(ETN1_BASE + ETN_MADR));
> + writel(0x00000001, (void *)(ETN1_BASE + ETN_MCMD));
> + detect_phy_wait();
> +
> + value = readl((void *)(ETN1_BASE + ETN_MRDD));
> + writel(0x00000000, (void *)(ETN1_BASE + ETN_MCMD));
> + return value;
> +}
> +
> +/* do a software reset on the phy */
> +static int detect_phy_softreset(u8 phyaddr)
> +{
> + int i, rc;
> +
> + debug("board detect: softreset PHY @0x%02x ", phyaddr);
> +
> + /*
> + * reset power down bit and set autonegotiation in
> + * phy basic control register 0
> + */
> + detect_phy_write(phyaddr, 0x00, 0x1200);
> +
> + /* set reset bit in phy basic control register */
> + detect_phy_write(phyaddr, 0x00, detect_phy_read(phyaddr, 0x00)
> + | (1 << 15));
> + udelay(260); /* HW ref (pg. 51): 256us, IEEE <= 500ms */
> +
> + /* Check for bit reset */
> + for (i = 0; i < 1000; i++) {
> + rc = detect_phy_read(phyaddr, 0x00);
> + if (!(rc & (1 < 11))) {
> + debug("OK\n");
> + return 0;
> + }
> + }
> +
> + debug("timed out!\n");
> + return -1;
> +}
> +
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +
> +ifndef CONFIG_SYS_PSRAM
> +# SDRAM
> +TEXT_BASE = 0x20780000
> +else
> +# mobile pSRAM
> +TEXT_BASE = 0x90700000
> +endif
> +
> +PLATFORM_CPPFLAGS += -fPIC -fPIE -fno-jump-tables # -msingle-pic-base
could you explain why?
> +
> +ifneq ($(OBJTREE),$(SRCTREE))
> +# We are building u-boot in a separate directory, use generated
> +# .lds script from OBJTREE directory.
> +LDSCRIPT := $(OBJTREE)/board/$(BOARDDIR)/u-boot.lds
> +endif
> diff --git a/board/dspg/firetux/firetux.c b/board/dspg/firetux/firetux.c
> new file mode 100644
> index 0000000..52f0ad1
> --- /dev/null
> +++ b/board/dspg/firetux/firetux.c
> @@ -0,0 +1,413 @@
> +/*
> + * firetux board specific setup
> + *
> + * (C) Copyright 2007-2009, emlix GmbH, Germany
> + * Juergen Schoew <j...@emlix.com>
> + *
> + * (C) Copyright 2008, DSPG Technologies GmbH, Germany
> + * (C) Copyright 2007, NXP Semiconductors Germany GmbH
> + * Matthias Wenzel, <n...@mazzoo.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <status_led.h>
> +#include "firetux.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/* functions for ethernet initialization */
> +extern int ip3912_eth_initialize(unsigned char nr, unsigned int etn_base,
> + unsigned int phy_base, unsigned char phy_addr, unsigned char rmii);
> +extern int ip3912_miiphy_initialize(bd_t *bis);
> +
> +#ifdef CONFIG_SHOW_BOOT_PROGRESS
> +void show_boot_progress(int progress)
> +{
> + printf("Boot reached stage %d\n", progress);
> +}
> +#endif
> +
> + writel(31, (void *)PNX8181_INTC_PRIOMASK_IRQ);
> + writel(31, (void *)PNX8181_INTC_PRIOMASK_FIQ);
> +
> + for (i = 1; i < 67; i++)
> + PNX8181_DISABLEIRQ(i);
> +
> + writel(readl((void *)PNX8181_CGU_GATESC) & 0xfdd7becd,
> + (void *)PNX8181_CGU_GATESC);
> +}
soc or board specifiy?
> +
> +/* Ethernet */
> +void firetux_sysmux_config_rmii(void)
> +{
> + /* config gpio c15 and c16 for RMII */
> + writel((readl((void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX4))
> + & ~(0x3 << 0)), (void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX4));
> + writel((readl((void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX5))
> + & ~(0x3 << 30)), (void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX5));
> +}
soc or board specifiy?
> +
> +void firetux_sysmux_config_etn1(void)
> +{
> + /* config gpio c0 and c6 for ETN1 */
> + writel((readl((void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX4))
> + & 0xffffc000), (void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX4));
> +}
soc or board specifiy?
> +
> +void firetux_sysmux_config_etn2(void)
> +{
> + /* config gpio c7 and c13 for ETN2 (alternative config for sd-card) */
> + writel((readl((void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX4))
> + & 0xf0003fff), (void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX4));
> +}
soc or board specifiy?
> +
> +int board_eth_init(bd_t *bis)
soc or board specifiy?
> +{
> + int rc = 0;
> +
> +/*
> + * priority setting for ETN over CPU for SDRAM access
> + * enable port-aging with priority for ETN
> + */
> +#ifdef CONFIG_SYS_ETHER_FAIR_SCHEDULE
> + /*
> + * be fair: ETN and CPU are both high priority, but ETN gets
> + * higher priority and a much lower ageing penatly to get
> + * much more accesses to RAM
> + */
> + writel(0x80000121, (void *)(PNX8181_SDI_SCHED + PNX8181_SCHED0));
> + writel(0xffff0100, (void *)(PNX8181_SDI_SCHED + PNX8181_SCHED1));
> + writel(0x00030131, (void *)(PNX8181_SDI_SCHED + PNX8181_SCHED2));
> +#else
> + /*
> + * highly prioritise the ETN engine and lower CPU priority
> + * to archive a better network thoughput
> + */
> + writel(0xffff0020, (void *)(PNX8181_SDI_SCHED + PNX8181_SCHED0));
> + writel(0xffff0000, (void *)(PNX8181_SDI_SCHED + PNX8181_SCHED1));
> + writel(0xffff0031, (void *)(PNX8181_SDI_SCHED + PNX8181_SCHED2));
> +#endif
> +
> + /* increase priority for SCRAM access at AHB of descriptors */
> + writew(7, (void *)(PNX8181_SC_ARB_BASE + PNX8181_SC_ARB_CFG2));
> + writew(7, (void *)(PNX8181_SC_ARB_BASE + PNX8181_SC_ARB_CFG3));
> +
> + /*
> + * init ETN clocks
> + *
> + * set ETNREFCLK to internal CGU clock, assuming a 13.824MHz crystal
> + * for other xtals see NXP's validation tests,
> + * lib/tools/source/swift_tools.c
> + */
> + writel((15 << 9) | (62 << 3) | 3, (void *)PNX8181_CGU_PER2CON);
> +
> + /* turn on PLL */
> + writel(readl((void *)PNX8181_CGU_PER2CON) | 0x00010000,
> + (void *)PNX8181_CGU_PER2CON);
> + /* wait for PLL lock */
> + while (!(readl((void *)PNX8181_CGU_PER2CON) & 0x00020000))
> + ;
> +
> + /* ungate ETN clocks */
> + writel(readl((void *)PNX8181_CGU_PER2CON) | 0x00802000,
> + (void *)PNX8181_CGU_PER2CON);
> +
> + /* register ip3912 mii interface */
> + ip3912_miiphy_initialize(gd->bd);
> +
> + /* register ethernet devices */
> + switch (get_boardrevision()) {
> + case 1:
> + case 2:
> + firetux_sysmux_config_rmii();
> + firetux_sysmux_config_etn1();
> + firetux_sysmux_config_etn2();
> + /* phys are at addr 0x1 & 0x2 at RMII phybus */
> + rc |= ip3912_eth_initialize(0, CONFIG_IP3912_ETN1_BASE,
> + CONFIG_IP3912_ETN1_BASE, 0x01, 1);
> + rc |= ip3912_eth_initialize(1, CONFIG_IP3912_ETN2_BASE,
> + CONFIG_IP3912_ETN1_BASE, 0x02, 1);
> + break;
> + case 3:
> + case 4:
> + firetux_sysmux_config_rmii();
> + firetux_sysmux_config_etn1();
> + firetux_sysmux_config_etn2();
> + /* phys are at addr 0x1e & 0x1d at RMII phybus */
> + rc |= ip3912_eth_initialize(0, CONFIG_IP3912_ETN1_BASE,
> + CONFIG_IP3912_ETN1_BASE, 0x1e, 1);
> + rc |= ip3912_eth_initialize(1, CONFIG_IP3912_ETN2_BASE,
> + CONFIG_IP3912_ETN1_BASE, 0x1d, 1);
> + break;
> + default:
> + return -1;
> + }
> + return rc;
> +}
> +
> +/*
> + * Miscellaneous platform dependent initialisations
> + */
> +
> +int board_init(void)
> +{
> + /* arch number of Firetux Platform Boards */
> + gd->bd->bi_arch_number = MACH_TYPE_PNX8181;
> +
> + /* adress of boot parameters / atags */
> + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
> +
> + /* release the RSTAPU and RSTEXT signal which keeps the PHYs in reset */
> + writel(readw((void *)PNX8181_WDRUCON) | 0x0009,
> + (void *)PNX8181_WDRUCON);
> + /* lower VDDIO to Vbgp * 2.44 (typ. 3.05V) */
> + writel(0x0079, (void *)PNX8181_DAIF_RVDDC);
> +
> + /* select TXD2 for GPIOa11 and select RXD2 for GPIOa1 */
> + writel(((readl((void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX0))
> + & 0xff3ffff3) | 0x00400004),
> + (void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX0));
> + /* select ETN for GPIOc0-16 */
> + writel(readl((void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX5))
> + & 0xfffffffc,
> + (void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX5));
> + writel(readl((void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX4))
> + & 0x30000000,
> + (void *)(PNX8181_SCON_BASE + PNX8181_SYSMUX4));
> +
> + /* use clk26m and fract-n for UART2 */
> + writew(((1 << 7) | (1 << 1)),
> + (void *)(PNX8181_UART2_BASE + PNX8181_UART_FDIV_CTRL));
> + writew(0x5F37, (void *)(PNX8181_UART2_BASE + PNX8181_UART_FDIV_M));
> + writew(0x32C8, (void *)(PNX8181_UART2_BASE + PNX8181_UART_FDIV_N));
> +
> + board_detect();
> +
> + firetux_gpio_init();
> +
> + icache_enable();
> + dcache_enable();
> +
> +#ifdef CONFIG_CMD_NAND
> + firetux_nandflash_init();
> +#else
> + firetux_norflash_init();
> +#endif
> +
> + firetux_irq_disable();
> +
> + return 0;
> +}
> +
> +int firetux_keystatus(int key)
> +{
> + int ret = 0;
> +
> + switch (key) {
> + case 1: /* GPIOA2 */
> + ret = get_gpioa(2);
> + break;
> + case 2: /* GPIOA10 */
> + ret = get_gpioa(10);
> + break;
> + default:
> + ret = -1;
> + break;
> + }
> +
> + return ret;
> +}
> +
> +void firetux_check_bootkey(void)
> +{
> + int i = 0, abort = 0;
> +
> + while ((abort == 0) && (i < 500)) {
> + if (firetux_keystatus(2) == 1) {
> + setenv("bootcmd", "run bootcmd1");
> + firetux_set_led(2, 0);
> + abort = 1;
> + }
> + i++;
> + udelay(10000);
> + }
> + if (abort == 0) {
> + setenv("bootcmd", "run bootcmd2");
> + puts("using alternative bootcmd\n");
> + firetux_set_led(2, 1);
> + }
> +}
> +
> +int misc_init_r(void)
> +{
> + if (get_boardrevision() > 1) /* ez_mcp_pnx8181 has no keys */
> + firetux_check_bootkey();
> +
> + setenv("verify", "n");
> + return 0;
> +}
> +
> +#if defined(CONFIG_DISPLAY_CPUINFO)
> +int print_cpuinfo(void)
soc or board specifiy?
> +{
> + unsigned int sysver, cgu_sccon, armclk, hclk;
> +
> + puts("CPU: ");
> + sysver = readw((void *)PNX8181_REG_SC_SYSVER);
> + printf("PNX8181-%d%c %s-ARM926EJ-S(ARMv5TEJ) ",
> + ((sysver >> 4) & 0xf), ((sysver & 0xf) + 64),
> + (((sysver >> 8) & 0xf) == 1) ? "OM6xxx" : "unknown");
> +
> + cgu_sccon = readw((void *)PNX8181_CGU_SCCON);
> +
> + /* armclk = bbcki * nsc / msc / ksc */
> + armclk = 13824 * (((cgu_sccon >> 3) & 0x3f) + 1)
> + / ((cgu_sccon & 0x7) + 1)
> + / (((cgu_sccon >> 10) & 0x3) + 1);
> + hclk = armclk / (((cgu_sccon >> 12) & 0xf) + 1);
> +
> + printf("@ %dMHz(armclk), %dMHz(hclk)\n",
> + (armclk / 1000), (hclk / 1000));
> + return 0;
> +}
> +#endif
> +
> +#if defined(CONFIG_DISPLAY_BOARDINFO)
> +int checkboard(void)
> +{
> + puts("Board: ");
> +
> + switch (get_boardrevision()) {
> + case 1:
> + puts("EZ_MCP_PNX8181\n");
> + break;
> + case 2:
> + puts("Vega_PNX8181_BaseStation Platform III-a\n");
> + break;
> + case 3:
> + puts("Vega_PNX8181_BaseStation Platform III-b\n");
> + break;
> + case 4:
> + puts("Vega_PNX8181_BaseStation Platform III-c\n");
> + break;
> + case 0:
> + default:
> + puts("unknown PNX8181 board\n");
> + break;
> + }
> +
> + return 0;
> +}
> +#endif
> +
> +int dram_init(void)
> +{
> + int reg;
> +
> + reg = readl((void *)PNX8181_SDI_CFG_1);
> + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> + gd->bd->bi_dram[0].size = 1 << (
> + (reg & 0x3) + /* dram width 8, 16, 32, 64 */
> + (((reg & 0x30) >> 4) + 8) + /* columns 8, 9, 10, 11 */
> + (((reg & 0x700) >> 8) + 9) + /* rows 9 .. 16 */
> + ((reg & 0x3000) >> 12)); /* nr banks 1, 2, 4 */
> +
> + return 0;
> +}
> diff --git a/board/dspg/firetux/firetux.h b/board/dspg/firetux/firetux.h
> new file mode 100644
> index 0000000..0196197
> --- /dev/null
> +++ b/board/dspg/firetux/firetux.h
> @@ -0,0 +1,144 @@
> +/*
> + * firetux board specific defines
> + *
> + * (C) Copyright 2007-2009, emlix GmbH, Germany
> + * Juergen Schoew <j...@emlix.com>
> + *
> + * (C) Copyright 2008, DSPG Technologies GmbH, Germany
> + * (C) Copyright 2007, NXP Semiconductors Germany GmbH
> + * Matthias Wenzel, <n...@mazzoo.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/*
> + * Boardrevisions:
> + * 0: unknown PNX8181 board
> + * 1: EZ_MCP_PNX8181
> + * 2: Vega_PNX8181_BaseStation Platform III-a
> + * 3: Vega_PNX8181_BaseStation Platform III-b
> + * 4: Vega_PNX8181_BaseStation Platform III-c
> + */
> +#define CONFIG_MAX_BOARDREVISIONS 4
> +enum firetux_revisions {
> + Any_PNX8181_BaseStation = -1,
> + UNKNOWN_PNX8181 = 0,
> + EZ_MCP_PNX8181,
> + VEGA_BASESTATION_IIIA,
> + VEGA_BASESTATION_IIIB,
> + VEGA_BASESTATION_IIIC,
> +};
> +
> +/* watchdog control register */
> +#define PNX8181_WDRUCON 0xc2203000
soc or board specifiy?
> +
> +/* digital to analog interface */
> +#define PNX8181_DAIF_RVDDC 0xc2000000
soc or board specifiy?
and so on please check
btw could you split this patch to simplify it's review
Best Regards,
J.
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