Stefan et al, I am trying to troubleshoot a weird PCIe problem on a PPC460GT based target, and it is getting curiouser and curiouser.
There is a tlb overlap I mentioned in an earlier email; on top of that there are some things happening in cpu/ppc4xx/4xx_pcie.c which I also find hard to understand: there is a static function pcie_get_base(), which returns a value as in address = pcie_get_base(hose, devfn) there are two instances of this, in both cases `address' is never used. The CONFIG_SYS_PCIE0_XCFGBASE constant (and its counterparts for other PCIe ports) is defined and used in the code, and gets a TLB entry assigned, but I can't find a place where it is programmed into the CPU - how does it know where this section is?! I have several different targets with different PCIe components, but all using the same base CPU subsystem design, and on some of them PCIe components misbehave, namely, PCIe memory read transactions fail with a machine check after a timeout, even though the PCIe side of things is fine (when looking with a protocol analyzer). Any insight/explanations/suggestions would be highly appreciated, TIA, vadim _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
