On Monday 01 December 2008, Leon Woestenberg wrote: > >> Now, if I re-program the end-point FPGA during the u-boot boot > >> time-out, Linux will recognize the end-point. > > > > It's possible that either the reset in between goes bonkers or something > > else causes your FPGA to stop responding. It looks like a programming > > problem with the FPGA to me. > > I have verified that the end point does not receive any kind of reset. > > Also, this problem only happens on the Canyonlands board; on x86 and > powerpc MPC8315E it remains properly working after soft/hard resets, > u-boot init etc.
This could be because only the 4xx Linux PCI(e) driver really resets the endpoint (PHY reset). But you seem to have analyzed this already. > Could it be u-boot overwrites a too large payload into the config > space or something similar, which makes subsequent accesses fail? Not sure. I suggest that you disable the PCI(e) support in U-Boot to see if Linux behaves differently on a non-pre-initialized endpoint. Best regards, Stefan ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: [EMAIL PROTECTED] ===================================================================== _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
