Change the MIMC200 startup code to use the built-in (rather than
hard-coded) funtions for setting up gclk outputs.
We'll also move the code to the new, more-appropriate
board_postclk_init() routine.
Signed-off-by: Mark Jackson <[EMAIL PROTECTED]>
---
board/mimc/mimc200/mimc200.c | 14 ++++++++------
1 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c
index ec83b9d..62c0943 100644
--- a/board/mimc/mimc200/mimc200.c
+++ b/board/mimc/mimc200/mimc200.c
@@ -30,8 +30,6 @@
#include <asm/arch/portmux.h>
#include <lcd.h>
-#define SM_PM_GCCTRL 0x0060
-
DECLARE_GLOBAL_DATA_PTR;
static const struct sdram_config sdram_config = {
@@ -83,10 +81,6 @@ int board_early_init_f(void)
portmux_select_gpio(PORTMUX_PORT_C, 1 << 18,
PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
- /* GCLK0 - 10MHz clock */
- writel(0x00000004, (void *)SM_BASE + SM_PM_GCCTRL);
- portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30, PORTMUX_FUNC_A, 0);
-
udelay(5000);
/* release phys reset */
@@ -132,6 +126,14 @@ int board_early_init_r(void)
return 0;
}
+int board_postclk_init(void)
+{
+ /* Use GCLK0 as 10MHz output */
+ gclk_enable_output(0, PORTMUX_DRIVE_LOW);
+ gclk_set_rate(0, GCLK_PARENT_OSC0, 10000000);
+ return 0;
+}
+
/* SPI chip select control */
#ifdef CONFIG_ATMEL_SPI
#include <spi.h>
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