Introducing 64-bit (36-bit) support for the MPC8641HPCN
failed to accomodate the other two 86xx boards.
Introduce definitions for CONFIG_SYS_CCSRBAR_PHYS_{LOW,HIGH}
CONFIG_SYS_CCSR_DEFAULT_DBAT{U,L} and CONFIG_SYS_CCSR_DEFAULT_IBAT{U,L}
with nominal 32-bit values.Signed-off-by: Jon Loeliger <[EMAIL PROTECTED]> Acked-by: Becky Bruce <[EMAIL PROTECTED]> --- Guys, I guess this is sort of a pass-the-brown-paper-bag patch. I swear I built these boards earlier, and they built fine. But clearly, there is a problem here that needs to be fixed. Sorry, jdl include/configs/MPC8610HPCD.h | 14 ++++++++++++++ include/configs/sbc8641d.h | 14 ++++++++++++++ 2 files changed, 28 insertions(+), 0 deletions(-) diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index f2fe4a6..5685027 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -81,6 +81,9 @@ #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 + #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) @@ -388,6 +391,17 @@ #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) +#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ + | BATL_PP_RW | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ + | BATU_BL_1M | BATU_VS | BATU_VP) +#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ + | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU +#endif + /* * BAT4 32M Cache-inhibited, guarded * 0xe200_0000 1M PCI-Express 2 I/O diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 45d8179..fa97827 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -104,6 +104,9 @@ #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 + #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) #define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) @@ -433,6 +436,17 @@ #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) +#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ + | BATL_PP_RW | BATL_CACHEINHIBIT \ + | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ + | BATU_BL_1M | BATU_VS | BATU_VP) +#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ + | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU +#endif + /* * BAT4 32M Cache-inhibited, guarded * 0xe200_0000 16M PCI-Express 1 I/O -- 1.6.0.4.761.g47577 _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
