The bits in ppc440.h for the SDR0_DDRCFG register are incorrect. The register is numbered in big-endian mode, so for example, the LT2 bit (bit 23) should be represented as 0x00000100 rather than 0x01000000.
Signed-off-by: Steven A. Falco <[EMAIL PROTECTED]> --- diff --git a/include/ppc440.h b/include/ppc440.h index c581f1b..520b0d9 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -174,13 +174,13 @@ #define sdr_ddrdl 0x00e0 #else #define sdr_cfg 0x00e0 -#define SDR_CFG_LT2_MASK 0x01000000 /* Leakage test 2*/ -#define SDR_CFG_64_32BITS_MASK 0x01000000 /* Switch DDR 64 bits or 32 bits */ +#define SDR_CFG_LT2_MASK 0x00000100 /* Leakage test 2*/ +#define SDR_CFG_64_32BITS_MASK 0x00000080 /* Switch DDR 64 bits or 32 bits */ #define SDR_CFG_32BITS 0x00000000 /* 32 bits */ -#define SDR_CFG_64BITS 0x01000000 /* 64 bits */ -#define SDR_CFG_MC_V2518_MASK 0x02000000 /* Low VDD2518 (2.5 or 1.8V) */ +#define SDR_CFG_64BITS 0x00000080 /* 64 bits */ +#define SDR_CFG_MC_V2518_MASK 0x00000040 /* Low VDD2518 (2.5 or 1.8V) */ #define SDR_CFG_MC_V25 0x00000000 /* 2.5 V */ -#define SDR_CFG_MC_V18 0x02000000 /* 1.8 V */ +#define SDR_CFG_MC_V18 0x00000040 /* 1.8 V */ #endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */ #define sdr_ebc 0x0100 #define sdr_uart0 0x0120 /* UART0 Config */ -- 1.6.0.2 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
