- Use readx/writex instead of direct pointer access
- Replace hardcoded values by macros
- Minor space to tab conversion
No functional change.
Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>
---
board/omap3/beagle/beagle.c | 78 +++++++++++++++++++-------------
board/omap3/overo/overo.c | 90 ++++++++++++++++++++++---------------
include/asm-arm/arch-omap3/omap3.h | 70 ++++++++++++++++++++++++++++
3 files changed, 171 insertions(+), 67 deletions(-)
Index: u-boot-arm/board/omap3/beagle/beagle.c
===================================================================
--- u-boot-arm.orig/board/omap3/beagle/beagle.c
+++ u-boot-arm/board/omap3/beagle/beagle.c
@@ -3,12 +3,12 @@
* Texas Instruments, <www.ti.com>
*
* Author :
- * Sunil Kumar <[EMAIL PROTECTED]>
- * Shashi Ranjan <[EMAIL PROTECTED]>
+ * Sunil Kumar <[EMAIL PROTECTED]>
+ * Shashi Ranjan <[EMAIL PROTECTED]>
*
* Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <[EMAIL PROTECTED]>
- * Syed Mohammed Khasim <[EMAIL PROTECTED]>
+ * Richard Woodruff <[EMAIL PROTECTED]>
+ * Syed Mohammed Khasim <[EMAIL PROTECTED]>
*
*
* See file CREDITS for list of people who contributed to this
@@ -56,41 +56,59 @@ int board_init(void)
/******************************************************************************
* Routine: misc_init_r
- * Description: Init ethernet (done here so udelay works)
+ * Description: Configure power supply
*****************************************************************************/
int misc_init_r(void)
{
unsigned char byte;
+ unsigned int *gpio5_base = (unsigned int *)OMAP34XX_GPIO5_BASE;
+ unsigned int *gpio6_base = (unsigned int *)OMAP34XX_GPIO6_BASE;
#ifdef CONFIG_DRIVER_OMAP34XX_I2C
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
- /* set vaux3 to 2.8V */
- byte = 0x20;
- i2c_write(0x4B, 0x7A, 1, &byte, 1);
- byte = 0x03;
- i2c_write(0x4B, 0x7D, 1, &byte, 1);
-
- /* set vpll2 to 1.8V */
- byte = 0xE0;
- i2c_write(0x4B, 0x8E, 1, &byte, 1);
- byte = 0x05;
- i2c_write(0x4B, 0x91, 1, &byte, 1);
+
+ /*
+ * Configure OMAP3 supply voltages in power management
+ * companion chip.
+ */
+
+ /* set VAUX3 to 2.8V */
+ byte = DEV_GRP_P1;
+ i2c_write(PWRMGT_ADDR_ID4, VAUX3_DEV_GRP, 1, &byte, 1);
+ byte = VAUX3_VSEL_28;
+ i2c_write(PWRMGT_ADDR_ID4, VAUX3_DEDICATED, 1, &byte, 1);
+
+ /* set VPLL2 to 1.8V */
+ byte = DEV_GRP_ALL;
+ i2c_write(PWRMGT_ADDR_ID4, VPLL2_DEV_GRP, 1, &byte, 1);
+ byte = VPLL2_VSEL_18;
+ i2c_write(PWRMGT_ADDR_ID4, VPLL2_DEDICATED, 1, &byte, 1);
/* set VDAC to 1.8V */
- byte = 0x20;
- i2c_write(0x4B, 0x96, 1, &byte, 1);
- byte = 0x03;
- i2c_write(0x4B, 0x99, 1, &byte, 1);
-
- byte = 0x33;
- i2c_write(0x4A, 0xEE, 1, &byte, 1);
-
- *((uint *) 0x49058034) = 0xFFFFFAF9;
- *((uint *) 0x49056034) = 0x0F9F0FFF;
- *((uint *) 0x49058094) = 0x00000506;
- *((uint *) 0x49056094) = 0xF060F000;
+ byte = DEV_GRP_P1;
+ i2c_write(PWRMGT_ADDR_ID4, VDAC_DEV_GRP, 1, &byte, 1);
+ byte = VDAC_VSEL_18;
+ i2c_write(PWRMGT_ADDR_ID4, VDAC_DEDICATED, 1, &byte, 1);
+
+ /* enable LED */
+ byte = LEDBPWM | LEDAPWM | LEDBON | LEDAON;
+ i2c_write(PWRMGT_ADDR_ID3, LEDEN, 1, &byte, 1);
+
+ /* Configure GPIOs to output */
+ writel(~((GPIO10) | GPIO9 | GPIO3 | GPIO2),
+ gpio6_base + OFFS(GPIO_OE));
+ writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+ GPIO15 | GPIO14 | GPIO13 | GPIO12),
+ gpio5_base + OFFS(GPIO_OE));
+
+ /* Set GPIOs */
+ writel(GPIO10 | GPIO9 | GPIO3 | GPIO2,
+ gpio6_base + OFFS(GPIO_SETDATAOUT));
+ writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+ GPIO15 | GPIO14 | GPIO13 | GPIO12,
+ gpio5_base + OFFS(GPIO_SETDATAOUT));
return 0;
}
@@ -98,8 +116,8 @@ int misc_init_r(void)
/******************************************************************************
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
*****************************************************************************/
void set_muxconf_regs(void)
{
Index: u-boot-arm/board/omap3/overo/overo.c
===================================================================
--- u-boot-arm.orig/board/omap3/overo/overo.c
+++ u-boot-arm/board/omap3/overo/overo.c
@@ -2,10 +2,10 @@
* Maintainer : Steve Sakoman <[EMAIL PROTECTED]>
*
* Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
- * Richard Woodruff <[EMAIL PROTECTED]>
- * Syed Mohammed Khasim <[EMAIL PROTECTED]>
- * Sunil Kumar <[EMAIL PROTECTED]>
- * Shashi Ranjan <[EMAIL PROTECTED]>
+ * Richard Woodruff <[EMAIL PROTECTED]>
+ * Syed Mohammed Khasim <[EMAIL PROTECTED]>
+ * Sunil Kumar <[EMAIL PROTECTED]>
+ * Shashi Ranjan <[EMAIL PROTECTED]>
*
* (C) Copyright 2004-2008
* Texas Instruments, <www.ti.com>
@@ -55,47 +55,65 @@ int board_init(void)
/******************************************************************************
* Routine: misc_init_r
- * Description: Init ethernet (done here so udelay works)
+ * Description: Configure power supply
*****************************************************************************/
int misc_init_r(void)
{
unsigned char byte;
+ unsigned int *gpio5_base = (unsigned int *)OMAP34XX_GPIO5_BASE;
+ unsigned int *gpio6_base = (unsigned int *)OMAP34XX_GPIO6_BASE;
#ifdef CONFIG_DRIVER_OMAP34XX_I2C
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
- /* set vaux2 to 2.8V */
- byte = 0x20;
- i2c_write(0x4B, 0x76, 1, &byte, 1);
- byte = 0x09;
- i2c_write(0x4B, 0x79, 1, &byte, 1);
-
- /* set vaux3 to 2.8V */
- byte = 0x20;
- i2c_write(0x4B, 0x7A, 1, &byte, 1);
- byte = 0x03;
- i2c_write(0x4B, 0x7D, 1, &byte, 1);
-
- /* set vpll2 to 1.8V */
- byte = 0xE0;
- i2c_write(0x4B, 0x8E, 1, &byte, 1);
- byte = 0x05;
- i2c_write(0x4B, 0x91, 1, &byte, 1);
+
+ /*
+ * Configure OMAP3 supply voltages in power management
+ * companion chip.
+ */
+
+ /* set VAUX2 to 2.8V */
+ byte = DEV_GRP_P1;
+ i2c_write(PWRMGT_ADDR_ID4, VAUX2_DEV_GRP, 1, &byte, 1);
+ byte = VAUX2_VSEL_28;
+ i2c_write(PWRMGT_ADDR_ID4, VAUX2_DEDICATED, 1, &byte, 1);
+
+ /* set VAUX3 to 2.8V */
+ byte = DEV_GRP_P1;
+ i2c_write(PWRMGT_ADDR_ID4, VAUX3_DEV_GRP, 1, &byte, 1);
+ byte = VAUX3_VSEL_28;
+ i2c_write(PWRMGT_ADDR_ID4, VAUX3_DEDICATED, 1, &byte, 1);
+
+ /* set VPLL2 to 1.8V */
+ byte = DEV_GRP_ALL;
+ i2c_write(PWRMGT_ADDR_ID4, VPLL2_DEV_GRP, 1, &byte, 1);
+ byte = VPLL2_VSEL_18;
+ i2c_write(PWRMGT_ADDR_ID4, VPLL2_DEDICATED, 1, &byte, 1);
/* set VDAC to 1.8V */
- byte = 0x20;
- i2c_write(0x4B, 0x96, 1, &byte, 1);
- byte = 0x03;
- i2c_write(0x4B, 0x99, 1, &byte, 1);
-
- byte = 0x33;
- i2c_write(0x4A, 0xEE, 1, &byte, 1);
-
- *((uint *) 0x49058034) = 0xFFFFFAF9;
- *((uint *) 0x49056034) = 0x0F9F0FFF;
- *((uint *) 0x49058094) = 0x00000506;
- *((uint *) 0x49056094) = 0xF060F000;
+ byte = DEV_GRP_P1;
+ i2c_write(PWRMGT_ADDR_ID4, VDAC_DEV_GRP, 1, &byte, 1);
+ byte = VDAC_VSEL_18;
+ i2c_write(PWRMGT_ADDR_ID4, VDAC_DEDICATED, 1, &byte, 1);
+
+ /* enable LED */
+ byte = LEDBPWM | LEDAPWM | LEDBON | LEDAON;
+ i2c_write(PWRMGT_ADDR_ID3, LEDEN, 1, &byte, 1);
+
+ /* Configure GPIOs to output */
+ writel(~((GPIO10) | GPIO9 | GPIO3 | GPIO2),
+ gpio6_base + OFFS(GPIO_OE));
+ writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+ GPIO15 | GPIO14 | GPIO13 | GPIO12),
+ gpio5_base + OFFS(GPIO_OE));
+
+ /* Set GPIOs */
+ writel(GPIO10 | GPIO9 | GPIO3 | GPIO2,
+ gpio6_base + OFFS(GPIO_SETDATAOUT));
+ writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
+ GPIO15 | GPIO14 | GPIO13 | GPIO12,
+ gpio5_base + OFFS(GPIO_SETDATAOUT));
return 0;
}
@@ -103,8 +121,8 @@ int misc_init_r(void)
/******************************************************************************
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
*****************************************************************************/
void set_muxconf_regs(void)
{
Index: u-boot-arm/include/asm-arm/arch-omap3/omap3.h
===================================================================
--- u-boot-arm.orig/include/asm-arm/arch-omap3/omap3.h
+++ u-boot-arm/include/asm-arm/arch-omap3/omap3.h
@@ -77,7 +77,7 @@
#define SYNC_32KTIMER_BASE 0x48320000
#define S32K_CR (SYNC_32KTIMER_BASE + 0x10)
-/* omap3 GPIO registers */
+/* OMAP3 GPIO registers */
#define OMAP34XX_GPIO1_BASE 0x48310000
#define OMAP34XX_GPIO2_BASE 0x49050000
#define OMAP34XX_GPIO3_BASE 0x49052000
@@ -85,6 +85,42 @@
#define OMAP34XX_GPIO5_BASE 0x49056000
#define OMAP34XX_GPIO6_BASE 0x49058000
+#define GPIO_OE 0x34
+#define GPIO_SETDATAOUT 0x94
+
+#define GPIO0 (0x1 << 0)
+#define GPIO1 (0x1 << 1)
+#define GPIO2 (0x1 << 2)
+#define GPIO3 (0x1 << 3)
+#define GPIO4 (0x1 << 4)
+#define GPIO5 (0x1 << 5)
+#define GPIO6 (0x1 << 6)
+#define GPIO7 (0x1 << 7)
+#define GPIO8 (0x1 << 8)
+#define GPIO9 (0x1 << 9)
+#define GPIO10 (0x1 << 10)
+#define GPIO11 (0x1 << 11)
+#define GPIO12 (0x1 << 12)
+#define GPIO13 (0x1 << 13)
+#define GPIO14 (0x1 << 14)
+#define GPIO15 (0x1 << 15)
+#define GPIO16 (0x1 << 16)
+#define GPIO17 (0x1 << 17)
+#define GPIO18 (0x1 << 18)
+#define GPIO19 (0x1 << 19)
+#define GPIO20 (0x1 << 20)
+#define GPIO21 (0x1 << 21)
+#define GPIO22 (0x1 << 22)
+#define GPIO23 (0x1 << 23)
+#define GPIO24 (0x1 << 24)
+#define GPIO25 (0x1 << 25)
+#define GPIO26 (0x1 << 26)
+#define GPIO27 (0x1 << 27)
+#define GPIO28 (0x1 << 28)
+#define GPIO29 (0x1 << 29)
+#define GPIO30 (0x1 << 30)
+#define GPIO31 (0x1 << 31)
+
/* base address for indirect vectors (internal boot mode) */
#define SRAM_OFFSET0 0x40000000
#define SRAM_OFFSET1 0x00200000
@@ -132,4 +168,36 @@
#define OMAP3EVM_V1 0x1
#define OMAP3EVM_V2 0x2
+/* I2C power management companion definitions */
+#define PWRMGT_ADDR_ID1 0x48
+#define PWRMGT_ADDR_ID2 0x49
+#define PWRMGT_ADDR_ID3 0x4A
+#define PWRMGT_ADDR_ID4 0x4B
+
+/* I2C ID3 (slave3) register */
+#define LEDEN 0xEE
+
+#define LEDAON (0x1 << 0)
+#define LEDBON (0x1 << 1)
+#define LEDAPWM (0x1 << 4)
+#define LEDBPWM (0x1 << 5)
+
+/* I2C ID4 (slave4) register */
+#define VAUX2_DEV_GRP 0x76
+#define VAUX2_DEDICATED 0x79
+#define VAUX3_DEV_GRP 0x7A
+#define VAUX3_DEDICATED 0x7D
+#define VPLL2_DEV_GRP 0x8E
+#define VPLL2_DEDICATED 0x91
+#define VDAC_DEV_GRP 0x96
+#define VDAC_DEDICATED 0x99
+
+#define DEV_GRP_P1 0x20
+#define DEV_GRP_ALL 0xE0
+
+#define VAUX2_VSEL_28 0x09
+#define VAUX3_VSEL_28 0x03
+#define VPLL2_VSEL_18 0x05
+#define VDAC_VSEL_18 0x03
+
#endif
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